Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
Reexamination Certificate
1999-02-18
2001-10-02
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Data flow based system
C712S001000, C712S018000
Reexamination Certificate
active
06298433
ABSTRACT:
This application claims priority of Russian Federation patent application 98102944 which was filed Feb. 20, 1998.
INTRODUCTION
The invention relates to computer science and, in particular, to computing devices that use dataflow control for information processing especially for use in high performance digital computing systems.
BACKGROUND OF THE INVENTION
There is a known computer system, which contains a processor and a group of processor devices, the inputs and outputs of which are connected with the corresponding inputs and outputs of a switching net. This system uses data flow control for the organization of the computation process. Effective loading of the processor devices is responsible for the level of performance. This is achieved by use of parallel instruction processing on all parts of the routine and is supported by a programmed organization of computations wherein the initial routine is mapped as a graph in which each node represents the functional dependence of one instruction on the performance of another instruction and the arcs define the directions of result transmission. Each of a set of processor devices, connected among themselves by a switching net, process the fixed local part of a routine. The processor devices work in parallel and the necessary synchronization between the parts of the processed routine is performed by means of data transmitted between the devices through the switching net. The absence of access of each of the processor devices to the entire routine and the necessity of mutual synchronization of its locally processed parts leads to inefficient losses of working time of the processor devices and hence to a reduction in performance of the system. (U.S. Pat. No. 4,814,978)
The known computer system that is closest to the invention disclosed in this application contains N processors, first and second switches, N modules of associative memory, a buffering block, first to third information inputs, control input and first and second information outputs. The first control outputs and address outputs of the i-th processor are connected correspondingly with the i-th input of the first group of control inputs and with the i-th input of the first group of address inputs of the first switch. The first and second information outputs of the i-th processor unit are connected with the corresponding i-th input of the first group of information inputs of the first switch. The first information, address, control and the second information, address and control inputs of the i-th processor are connected with the first and second information inputs of the system. The control input of the system is connected with the control input of the first switch and with the third control input of the i-th processor. The control output of the first switch is connected with the fourth control input of the i-th processor. The third information output of the processor is connected with the first information output of the system. The first control, first information, second control and second information outputs of the i-th group of exchange outputs of the second switch are connected correspondingly with the fifth control, third information, sixth control and fourth information inputs of the i-th processor. The first group of control outputs of the second switch is connected with the first group of control inputs of the buffering block. The second group of control outputs of the second switch is connected with the second group of control inputs of the buffering block. The control inputs of the second switch and of the buffering block and the first control input of each module of associative memory are connected with the control input of the system. The i-th inputs of the first and second groups of control inputs of the second switch are connected correspondingly with the second and third control outputs of the i-th processor. The seventh and eighth control inputs of the i-th processor are connected correspondingly with the i-th outputs of the first and second groups of control outputs of the buffering block. The third group of control outputs and the first group of information outputs of the buffering block are connected correspondingly with the third group of control inputs and the first group of information inputs of the second switch. The second group of information outputs of the buffering block is connected with the second information output of the system. The fourth group of control inputs of the second switch is connected with the fourth group of control outputs of the buffering block. The i-th input of the first group of information inputs of the buffering block is connected with the fourth and fifth information outputs of the i-th processor. The fourth control output of i-th processor is connected with the i-th input of the third group of control inputs of the buffering block. The third group of information outputs of the buffering block is connected with the second group of information inputs of the second switch. The first control output of the i-th module of associative memory is connected with the i-th input of the second group of control inputs of the first switch. The i-th output of the group of information outputs of the first switch is connected with the information input of the i-th module of associative memory. The information and second control outputs of the i-th module of associative memory are connected with the i-th inputs of the second group of information inputs and the fourth group of control inputs of the buffering block. The third group of information inputs of the buffering block is connected with the third information input of the system. And, the i-th output of the group of control outputs of the first switch is connected with the second control input of the i-th module of associative memory. (PCT/RU 96/00347)
This system provides information processing without any inter-processor exchange, hence, decreasing the time for program processing. Furthermore, this system allows the failure of one or more of the processors without interrupting the work of the system on the whole. A high level of performance is achieved due to the increased loading of the processors which results in a decrease in the time required for running routines. A high degree of parallelism is achieved automatically and the need to distribute groups of parallel processes from each routine among the processors is obviated.
However, this system fails to provide high performance in running routines, or parts of routines, which have a low level of inner parallelism. For example, the sequential performance of routine instructions is not executed as efficiently with this system as it is with a system that utilizes the traditional von Neumann principle of data processing.
Moreover, this device uses dataflow for control of the computation process and associative memory hardware for storage of data and results. The associative memory simultaneously performs the function of control means hardware. Accordingly, since there is no loss of time on the processes of memory distribution, performance increases.
However, the performance of the system depends directly on the associative memory and is defined by the rate of data output from associative memory in a unit of time. The number of operands output and ready for processing in a unit of time is defined by N=1/Tam, where Tam=time of work of associative memory from the moment of inquiry to the output of data.
The value Tam depends directly on the volume (or size) of associative memory. Since Tam, measured from the time of inquiry from a running routine, increases as the size of the associative memory increases, the performance of the device decreases as the size of the associative memory increases.
Thus, the device fails to achieve a high level of performance when large volumes of running routines with low levels of inner parallelism are processed.
SUMMARY OF THE INVENTION
It is an object of the invention to increase performance by decreasing the volume of associative memory while at the same time introducing the local use of dat
Burtsev Vsevolod Sergeevich
Erschov Vladimir K.
Fyodorov Vjacheslav B.
Koslov Lev A.
Nikolskaia Julia N.
Costa John G.
Lin Wen-Tai
Maung Zarni
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