Multiplex communications – Duplex – Communication over free space
Reexamination Certificate
1998-03-27
2004-06-15
Pham, Chi (Department: 2667)
Multiplex communications
Duplex
Communication over free space
Reexamination Certificate
active
06751201
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a data exchange system, and more particularly to a data exchange system to be used for a mobile communication base station applicable to high traffic. The invention relates further to a method of data exchange.
2. Description of the Related Art
A mobile communication base station is generally designed to have a plurality of central processing units (CPUs) for processing subscriber data to thereby conform to high traffic. A relation among the number of subscriber's loops M, subscriber data processing capability per a single central processing unit L, and the number of central processing units N is represented by the following equation.
M=L×N
A generally used data exchange system is explained hereinbelow with reference to
FIG. 1
which is a block diagram of a mobile communication base station including a generally used data exchange system.
First, data flow from a subscriber to public network is explained hereinbelow. As illustrated in
FIG. 1
, the m number of data about subscriber's loop is transmitted from a subscriber radio interface circuit
61
to each of n CPUs
1
-i (i=
1
to n). Data received
1
-i is processed in each of n CPUs and then transmitted to a parallel/serial (P/S) converting circuit
63
as parallel data PDTi (i=
1
to n). The parallel data is converted into the m number of serial data SDATj (j=
1
to m) by the P/S converting circuit
63
, and then, is line-exchanged in a line exchange circuit
64
. The thus line-exchanged serial data SDATj′ (j=
1
to m) is output to public lines
65
through a public network interface circuit
62
.
Data flow from public network to a subscriber is just opposite to the above-mentioned steps. The detail is omitted.
Hereinbelow is explained the function of a section encompassed with a broken line in FIG.
1
and including the P/S converting circuit
63
and the line exchange circuit
64
. Herein, suppose that data is transmitted from a subscriber toward public network. Parallel data PDTi (i=
1
to n) transmitted from a subscriber through a plurality of CPUs
1
-
1
to
1
-n is in a row, “D
11
-
17
”, “D
21
-
27
”, - - - , “DL
1
-L
7
”, “D′
11
-
17
”, - - - , as illustrated in FIG.
2
. The parallel data PDTi is temporarily stored in a buffer formed in the P/S converting circuit
63
, and then, is transmitted from the circuit
63
as the M number of serial data SDAT i
1
-iL wherein M=N×L.
The thus transmitted SDAT i
1
-iL is line-exchanged to a desired line by the line exchange circuit
64
. The thus line-exchanged M number of serial data is transmitted to the public network interface circuit
62
, and then, to the public lines
65
through the public network interface circuit
62
. Herein, SDAT i
1
to SDAT nL indicates the totally M number of data.
The structure of a first conventional data exchange system is explained hereinbelow with reference to FIG.
3
.
As illustrated in
FIG. 3
, the first conventional data exchange system is comprised of the P/S exchange circuit
63
and the line exchange circuit
64
. The P/S exchange circuit
63
includes a large-size dual port RAM
631
for storing therein data having been processed in the n CPUs
1
-
1
to
1
-n, a parallel/serial (P/S) converting section
632
, a timing generating circuit
633
, and a bus arbitrating circuit
634
for arbitrating a bus from the n CPUs. The line exchange circuit
64
includes a switching circuit
641
, and an exchange information transfer circuit
642
. Parts or elements corresponding to those in
FIG. 1
have been provided with the same reference numerals.
The dual port RAM
631
includes the m number of storage areas in which parallel data transmitted from the n number of CPUs
1
-
1
to
1
-n is to be stored, and further includes ports each of which faces the n number of CPUs and the P/S converting section
632
. Data is stored (or written) into or taken (or read) out of the dual port RAM
631
through the ports. The dual port RAM
631
is in communication with all of the n number of CPUs
1
-
1
to
1
-n through a common data bus DBUS, and receives addresses ADD from all of the n number of CPUs
1
-
1
to
1
-n.
The P/S converting section
632
converts parallel data PDT received from the dual port RAM
631
, into serial data at a timing defined by a timing signal TIM transmitted from the timing generating circuit
633
. The P/S converting section
632
transmits parallel address PAD to the dual port RAM
631
.
The timing generating circuit
633
produces timing signals TIM at a certain interval, and transmits it to the P/S converting section
632
for converting parallel data into serial data.
The switching circuit
641
connects serial data received therein to a designated public line in accordance with exchange information XC transmitted from the exchange information transfer circuit
642
.
The exchange information transfer circuit
642
receives the exchange information XC from an upstream system (not illustrated), and transmits the exchange information XC to the switching circuit
641
at a predetermined timing.
The bus arbitrating circuit
634
arbitrates requests transmitted from the n number of CPUs
1
-
1
to
1
-n for storing parallel data therein, and prevents data collision on a bus. Specifically, the bus arbitrating circuit
634
receives requests RQ
1
-RQn for occupying a bus from the n number of CPUs
1
-
1
to
1
-n, and transmits an allowance AK
1
-AKn to use a bus.
Hereinbelow is explained an operation of the first conventional data exchange system illustrated in
FIG. 3
, with reference to
FIG. 4
which is a time chart illustrating an operation of the first conventional data exchange system. Each of the n number of CPUs
1
-
1
to
1
-n, when having processed data, transmits the request RQ
1
-RQn for occupying the data bus DBUS of the dual port RAM
631
, to the bus arbitrating circuit
634
. The bus arbitrating circuit
634
having received those requests RQ
1
-RQn for occupying the data bus DBUS of the dual port RAM
631
transmits the allowance AK
1
-AKn to each of the CPUs in an order at which the requests RQ
1
-RQn have been received. Only CPU which received the allowance can transmit the processed data to the dual port RAM
631
through the data bus DBUS. The thus transmitted, processed data is stored in the dual port RAM
631
. The data having been stored in the dual port RAM
631
is taken out of the dual port RAM
631
as the parallel data PDT by the P/S converting section
632
in synchronization with the timing signals TIM transmitted from the timing generating circuit
633
for every one of the m number of lines in accordance with the parallel address PAD transmitted from the P/S converting section
632
. The thus taken-out parallel data PDT is converted into serial data in the P/S converting section
632
. The m number of data having been converted into serial data in the P/S converting section
632
is line-exchanged in the switching circuit
641
in accordance with the exchange information XC transmitted from the exchange information transfer circuit
642
and indicating where the data is transferred to. The thus line-exchanged data is transmitted to the public network interface circuit
62
as serial data SDAT
1
′ to SDATm′.
The switching circuit
641
carries out switch between input and output lines in such a manner as illustrated in FIG.
5
. Specifically, the switching circuit
641
converts data D
1
, D
2
and Dm received therein through input lines, into data D
1
′, D
2
′ and Dm′ to be output through output lines. As illustrated in
FIG. 5
, data D
1
′, D
2
′ and Dm′ correspond to data Dm, D
1
and D
2
, respectively.
FIG. 6
illustrates a second conventional data exchange system, including the P/S exchange circuit
63
and the line exchange circuit
64
. The illustrated data exchange system is different from the first conventional data exchange system illustrated in
FIG. 3
in that it includes
Dickstein Shapiro Morin & Oshinsky LLP.
Jones Prenell
NEC Corporation
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