Data error detection and correction system

Details Data error detection and correction system Data error detection and correction system

1994-10-14

1996-09-10

Gordon, Paul P.

Excavating

371 404, H03M 1300

Patent

active

055552501

ABSTRACT:
A system that performs error correction and detection of data read from memory in a computer system having a processor bus and a system bus. A pair of data buffers are used to interface between the memory and the processor data bus or the system data bus. Each data buffer receives half the data bits from the memory array, from the processor data bus, and from the system data bus. Each of the data buffers contains logic for performing error detection and correction. To enable error correction, check bits are generated by the data buffers in a write cycle to the memory. A feature of the present invention is that half the check bits are provided to one data buffer and the second half is provided to other data buffer. When a memory read cycle is performed, the retrieved check bits and data bits are examined according to the error correction algorithm to determine if a single bit correctable error has occurred. If so, the erroneous data bit is flipped. If a multiple bit error is detected, the microprocessor is interrupted to take appropriate remedial actions.

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Codes for High-Speed Memories II: Byte Error Correcting/Detecting Codes, .COPYRGT.1989 by T. R. N. Rao and E. Fujiwara, Published by Prentice-Hall, Inc.

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