Data error detection and correction for a shared SRAM

Details Data error detection and correction for a shared SRAM Data error detection and correction for a shared SRAM

1995-10-10

1997-03-11

Beausoliel, Jr., Robert W.

Excavating

371 102, G01R 3128, G11C 2900, G06F 1100

Patent

active

056110421

ABSTRACT:
An apparatus for correcting errors in information read from a memory unit, comprises a first and second memory, where primary and backup information are stored in predetermined addressable locations. The primary information and the backup information in corresponding locations are the same. A processor, commands a read of information stored in the memory unit, the read being a simultaneous read of the primary information and the corresponding backup information. A multiplexer, couples the output ports to the processor. The primary information read from the first and second memory and the backup information read from the first and second memory are coupled to the multiplexer. The first and second memory each indicate via a respective first and second error signal if an error is detected on the information just read from the first and second memory, respectively. Select logic determines whether the data in the first and second memory contains the primary or the backup information and generates the control signal to select the set of input ports to be the output of the multiplexer. The control signal selects the primary signal to be coupled to the processor if no error is indicated in the primary copy and selects the backup information to be coupled to the processor if an error is indicated in the primary copy and not the backup copy.

REFERENCES:
patent: 3668644 (1972-06-01), Looschen
patent: 3761903 (1973-09-01), Bird, Jr.
patent: 4404647 (1983-09-01), Jones
patent: 5251174 (1993-10-01), Hwang
patent: 5402377 (1995-03-01), Ohhata

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