Data error correcting/detecting system and apparatus compatible

Details Data error correcting/detecting system and apparatus compatible Data error correcting/detecting system and apparatus compatible

1992-03-17

1995-09-12

Envall, Jr., Roy N.

Excavating

371 402, G06F 1110

Patent

active

054504236

ABSTRACT:
Memory expansion using memory packages of different generations is performed without unnecessarily increasing the minimum memory capacity of a memory device and while obtaining a high error detecting ability and high reliability. In expanding the capacity of a memory device by using first generation 1M.times.1 bit IC memory packages, second generation 4M.times.4 bits IC memory packages, or third generation 16M.times.8 bits IC memory packages, the total code length is set to 40 bits, a 4's multiple, within a range longer than the total code length necessary for S4ED and shorter than the total code length necessary for S8ED, and a reduced code is used for enhancing the S8ED function. In this manner, wasteful first generation IC memory packages can be reduced in number, and the error detecting ability of a memory device using third generation memory packages can be retained substantially the same as that of a memory device using first generation memory packages.

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S. Kaneda, "A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System" Paper of the Institute of Electronic Communication Engineers of Japan. vol. J67 DNo. 5, May, 1984.

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