Data erasing method, and memory apparatus having data...

Details Data erasing method, and memory apparatus having data... Data erasing method, and memory apparatus having data...

2006-04-04

2006-04-04

Ngô, Ngan V. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185250, C365S185260, C365S185270, C365S185290, C257S316000

Reexamination Certificate

active

07023732

ABSTRACT:
The present invention is to propose an data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, a memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate is disclosed. In this case, the data erasing circuit boosts a potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate to make the potential of the control gate to a predetermined potential.

REFERENCES:
patent: 6307807 (2001-10-01), Sakui et al.
patent: 2001/0054737 (2001-12-01), Nakamura et al.
patent: 2000-294658 (2000-10-01), None

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