Static information storage and retrieval – Floating gate – Particular connection
Patent
1997-10-17
1998-09-08
Hoang, Huan
Static information storage and retrieval
Floating gate
Particular connection
36518522, 36518529, 365236, G11C 1604
Patent
active
058055100
ABSTRACT:
The total number of bits of irregular blocks is equal to the number of bits of one equal block. The memory cells of the irregular blocks are sequentially designated using an address counter used to designate the memory cells of equal blocks. An erase operation (including pre program and erase operations) starts from "verify". Only when "verify" is NG, the pre program and erase operations are performed. A means capable of fixing a verify result VERIOK at "1" (verify OK) is arranged to always set VERIOK at "1" for a non-select block of the irregular blocks, thereby preventing execution of the pre program and erase operations for the non-select block of the irregular blocks. Accordingly, in the boot block type, the same address counter is shared by the equal and irregular blocks to reduce the circuit scale.
REFERENCES:
patent: 5297096 (1994-03-01), Terada et al.
patent: 5590074 (1996-12-01), Akaogi et al.
patent: 5592415 (1997-01-01), Kato et al.
patent: 5602789 (1997-02-01), Endoh et al.
Kuriyama Masao
Miyakawa Tadashi
Saito Hidetoshi
Taura Tadayuki
Hoang Huan
Kabushiki Kaisha Toshiba
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