Data encryptor having a scalable clock

Details Data encryptor having a scalable clock Data encryptor having a scalable clock

1996-04-16

1997-09-23

Cain, David C.

Cryptography

Particular algorithmic function encoding

Nbs/des algorithm

380 38, H04K 100

Patent

active

056712847

ABSTRACT:
A method for encrypting and decrypting digital data. The digital data is initially latched by an input register. Sixteen separate cipher stages cascaded in series are used to encrypt the digital data. These cipher stages are operating at a maximum frequency limited only by the process technology. The encoded digital data from the last cipher stage is stored in an output register. The input and output registers are capable of being docked at an interface frequency that is different from that of the DES core's data frequency. After an appropriate number of cycles have elapsed, the output register is sampled. A programmable counter is used to indicate when the output register contains valid encrypted data.

REFERENCES:
patent: 5128959 (1992-07-01), Bruckert
patent: 5377264 (1994-12-01), Lee et al.

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