Data edge phase sorting circuits

Details Data edge phase sorting circuits Data edge phase sorting circuits

1991-02-05

1993-05-18

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

328 56, H03D 324

Patent

active

052127168

ABSTRACT:
Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line having a plurality of serially connected delay elements, each of which outputs a delay clock of different phase. The sorting circuit includes an extraction circuit coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit, which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks. Specific embodiments for the extraction circuit and non-sequential logic circuitry are depicted and described herein.

REFERENCES:
patent: 4746872 (1988-05-01), Yamagata

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