Data driver circuit for a dynamic random access memory...

Details Data driver circuit for a dynamic random access memory... Data driver circuit for a dynamic random access memory...

2011-01-18

2011-01-18

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S191000, C365S193000, C365S230080, C365S233100

Reexamination Certificate

active

07872937

ABSTRACT:
A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an input coupled to the output of the first latch (322), a control input for receiving a control signal, and an output. The extension logic circuit (324) selectively delays the output of the first latch (322) in response to the control signal. The second latch (330) has an input coupled to the output of the extension logic circuit (324), a clock input for receiving a second clock signal, and an output for providing an output data signal.

REFERENCES:
patent: 5373255 (1994-12-01), Bray et al.
patent: 5440515 (1995-08-01), Chang et al.
patent: 5857095 (1999-01-01), Jeddeloh et al.
patent: 6691214 (2004-02-01), Li et al.
patent: 6791889 (2004-09-01), Peterson
patent: 6930932 (2005-08-01), Rentschler
patent: 7038971 (2006-05-01), Chung
patent: 7061941 (2006-06-01), Zheng
patent: 7117381 (2006-10-01), Kim et al.
patent: 7184323 (2007-02-01), Fujisawa
patent: 7321525 (2008-01-01), Matsui
patent: 7457174 (2008-11-01), Braun et al.
patent: 7487378 (2009-02-01), Morein et al.
patent: 7518946 (2009-04-01), Iwasaki
patent: 2002/0147892 (2002-10-01), Rentschler et al.
patent: 2002/0147896 (2002-10-01), Rentschler et al.
patent: 2003/0021164 (2003-01-01), Yoo et al.
patent: 2004/0143775 (2004-07-01), Li et al.
patent: 2005/0197082 (2005-09-01), Agostinelli
patent: 2005/0204245 (2005-09-01), Lee et al.
patent: 2005/0243608 (2005-11-01), Lee
patent: 2006/0114742 (2006-06-01), Salmont et al.
patent: 2006/0133158 (2006-06-01), Shin
patent: 2006/0262613 (2006-11-01), Braun et al.
patent: 2007/0217559 (2007-09-01), Stott et al.
patent: 2009/0086562 (2009-04-01), Richards
patent: 2009/0244995 (2009-10-01), Searles et al.
patent: 2009/0244996 (2009-10-01), Searles et al.
patent: 2009/0244997 (2009-10-01), Searles et al.
patent: 2009/0296501 (2009-12-01), Searles
patent: 2008/063199 (2008-05-01), None
International Search Report in application No. PCT/US2009/003220 mailed Sep. 15, 2009, 12 pages.
“Double Data Rate (DDR) SDRAM Specification,” JESD79, Release 2, JEDEC Solid State Technology Association, JEDEC Standard, Electronics Industries Alliance, May 2002.
U.S. Appl. No. 12/059,613, Office Action mailed Apr. 7, 2010, 6 pages.
U.S. Appl. No. 12/059,593, Notice of Allowance mailed Apr. 9, 2010, 8 pages.
U.S. Appl. No. 12/059,653, Notice of Allowance mailed Apr. 29, 2010, 14 pages.
U.S. Appl. No. 12/059,653 Notice of Allowance mailed Aug. 10, 2010, 11 pages.
U.S. Appl. No. 12/059,593 Notice of Allowance mailed Jul. 23, 2010, 8 pages.
U.S. Appl. No. 12/127,059 Non-Final Office Action mailed Sep. 2, 2010, 8 pages.
U.S. Appl. No. 12/059,613 Final Office Action mailed Jul. 27, 2010, 9 pages.

Affiliated with

Also associated with

Rating

Data driver circuit for a dynamic random access memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data driver circuit for a dynamic random access memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data driver circuit for a dynamic random access memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2625460