Data driver circuit and delay-locked loop circuit

Details Data driver circuit and delay-locked loop circuit Data driver circuit and delay-locked loop circuit

2008-09-19

2011-10-04

Hjerpe, Richard (Department: 2629)

Computer graphics processing and selective visual display system

Display driving control circuitry

Reexamination Certificate

active

08031189

ABSTRACT:
A data driver circuit and a delay-locked loop (DLL) circuit that can operate normally in spite of errors, etc., caused when an analog data signal is applied to a display panel are provided. The data driver circuit receives a first data signal and a first clock signal and outputs a second data signal to be transmitted to a display panel. The data driver circuit includes a data driver for sampling the first data signal in response to a second clock signal and outputting the second data signal obtained by analog-converting the first data signal, a mask signal generator for generating a mask signal indicating presence within a predetermined time period measured from a point in time at which the second data signal begins to change, and a DLL for generating the second clock signal from the first clock signal. Here, there is a delay between the first and second clock signals, the delay changes according to a phase difference between the first and second clock signals, and the change in the delay according to the phase difference is prevented by the mask signal.

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