Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
2000-01-14
2003-02-25
Pan, Daniel H. (Department: 2756)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
C712S026000, C712S027000, C712S201000, C709S239000
Reexamination Certificate
active
06526500
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data driven type information processing systems, and more particularly, to a data driven type information processing system suitable for interconnecting a plurality of data driven type information processing devices into a multi-network form.
2. Description of the Background Art
In a von-Neumann type computer, various instructions are prestored as a program in a program storage unit. These instructions are read out for execution by a program counter, which sequentially designates addresses in the program storage unit.
In contrast, the data driven type information processing device is a kind of non-von-Neumann computer, which is free from the concept of such sequential execution of instructions by the program counter. In the data driven type information processing device, instructions become ready for execution once data to be operated are collected, and a plurality of instructions are executed in parallel. The device is advantageous in that time required for operation can be significantly reduced.
FIG. 13
is a block configuration diagram of a conventional data driven type processor.
FIGS. 14A
to
14
C illustrate field configurations of data packets to be processed in the data driven type processor shown in FIG.
13
.
FIG. 15
is a diagram showing an example of the contents stored in the program storage unit of FIG.
13
.
FIG. 16
shows a configuration of a system including a plurality of data driven type processors each as shown in FIG.
13
.
The data packet PA
1
shown in
FIG. 14A
includes a processor (PE) number
50
, a node number
51
, a left/right data flag
52
, an instruction code
53
, a generation number
54
, and a first operand
55
. The data packet PB
1
in
FIG. 14B
includes a second operand
56
in addition to the contents of data packet PA. The data packet PC
1
in
FIG. 14C
includes PE number
50
, node number
51
, generation number
54
, and first operand
55
.
Data driven type processor PEl in
FIG. 13
includes: branch units
20
and
25
that each input an applied data packet, compare contents of the input data packet with contents preset in an internal memory, and output the input data packet to an output destination that is selected in accordance with the result of comparison; junction units
21
and
27
that each input the data packets applied thereto and sequentially output the same; a firing control unit
22
; an operation processing unit
23
; a program storage unit
24
that prestores a data flow program as shown in
FIG. 15
; and an internal data buffering unit
26
.
Branch units
20
and
25
have internal memories
201
and
251
, respectively. Memories
201
and
251
each have a PE number that uniquely identifies the relevant data driven type processor PE
1
. This PE number is prestored by software or preset by an external terminal (not shown).
In operation, branch unit
20
determines whether PE number
50
of data packet PA
1
input from an input port IN and the PE number preset in memory
201
match with each other. If they match, branch unit
20
outputs input data packet PA
1
to junction unit
21
; if not, input data packet PA
1
goes to junction unit
27
. Junction unit
21
inputs both the data packet PA
1
output from branch unit
20
and the data packet PA
1
output from internal data buffer
26
, and sequentially outputs the input data packets PA
1
to firing control unit
22
, while controlling the stream of the data packets.
Firing control unit
22
detects two data packets, which are to constitute a pair for a binary operation instruction. In other words, two data packets PA having the same node numbers
51
and generation numbers
54
are waited for and, when the matching is complete (i.e., when the paired data are detected), the two data packets PA
1
are combined and output as a single data packet PB
1
to operation processing unit
23
. At this time, respective one of the first operands
55
of the two data packets PA
1
detected as the paired data is set to either one of the first and second operands
55
and
56
of data packet PB
1
, depending on the left/right data flags
52
of the respective data packets PA
1
detected as the paired data.
Operation processing unit
23
performs, according to instruction code
53
of input data packet PB
1
, operation for corresponding first or second operand
55
or
56
, and outputs data packet PC
1
, having a result of the operation stored therein as first operand
55
, to program storage unit
24
.
Program storage unit
24
prestores a data flow program consisting of a plurality of processor numbers PE, a plurality of node numbers ND, a plurality of instruction codes OP and a plurality of left/right data flags DF, as shown in FIG.
15
. Program storage unit
24
inputs data packet PC applied thereto, and reads out, by addressing based on the node number
51
of the input packet PC
1
, a subsequent processor number PE, a subsequent node number ND, a subsequent instruction code OP and a subsequent left/iight data flag DF from the data flow program. The read out processor number PE and node number ND are set as PE number
50
and node number
51
of the input data packet PC
1
, and the read out instruction code OP and left/right data flag DF are added to the input data packet PC
1
as instruction code
53
and left/right data flag
52
, respectively (generation number
54
remains unchanged). Data packet PA
1
is thus obtained, which is then output to branch unit
25
. This is called “instruction fetch.”
Branch unit
25
inputs data packet PA
1
output from program storage unit
24
, and determines whether PE number
50
of the input data packet PA
1
and the PE number within the memory
251
match with each other. If they match, branch unit
25
outputs input data packet PA
1
to internal data buffering unit
26
. If they do not mach, data packet PA
1
is output to junction unit
27
.
Internal data buffering unit
26
inputs data packets PA
1
applied thereto, and sequentially outputs them to junction unit
21
.
Thus, the data packets are transmitted along junction unit
21
→ firing control unit
22
→ operation processing unit
23
→ program storage unit
24
→ branch unit
25
, and processing for one node in a data flow graph, which is expressed by the data flow program prestored in program storage unit
24
, is completed.
The data flow graph (or, the data flow program) is carried out by repeating the paired data detection, the operation processing and the instruction fetch for the data packets, as explained above.
One way to improve processing performance of the above-described data driven type information processor is to incorporate a plurality of data driven type processors PE within a single system.
The Japanese Patent Laying-Open No. 6-259583 discloses a system consisting of a plurality of data driven type processors
1
to
4
, as shown in
FIG. 16
, wherein a method of interconnecting the processors is disclosed. In this reference, the processors are connected with one another via processor-to-processor transmission paths. In operation, a data packet is transmitted through the transmission paths to a processor by which the data packet itself is to be processed. Here, an appropriate, short route is chosen therebetween, according to processor designating information (i.e., the PE number) within the data packet that designates its relevant processor, and a prescribed condition. That is, each processor within the system includes memories
201
and
251
, as shown in
FIG. 13
, which store information for uniquely identifying the processor itself (i.e., the PE number). Thus, the data packets are processed in respective processors, while the processor designating information (the PE number) within each data packet and the PE number set in each processor are compared with each other.
In an effort to realize an integrated circuit of data driven type processors, the operation processing capability has been steadily improved, and the number of processors forming one system h
Muramatsu Tsuyoshi
Onozaki Manabu
Yumoto Manabu
Pan Daniel H.
Sharp Kabushiki Kaisha
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