Patent
1996-08-20
1999-06-29
Lane, Jack A.
39580025, G06F 1300
Patent
active
059180633
ABSTRACT:
A data flow information processing apparatus includes one or a plurality of data driven type processors for processing data packets based on a data flow program, one or a plurality of memories accessed by these processors, and a router receiving data packets processed by these data processors for selecting a path for selectively applying the data packet to any of the one or the plurality of memories. More preferably, a first router includes an address calculating unit for calculating the address based on the content of the data packet, and a branching unit for branching the path of the data packet based on the calculated address. The data packet includes a generation number allotted in accordance with the order of input time and data. The address calculating unit includes a unit for calculating a modified address by modifying the generation number based on the data. The address modifying unit may include a circuit for modifying the generation number with a prescribed global offset, and a circuit for calculating a locally offset address by further modifying the generation number with the data included in the applied data packet.
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"An Evaluation of Parallel-Processing in the Dynamic Data-Driven Type Processor" Translation of JP 64-21538.
Miyama Ryuji
Miyata Souichi
Muramatsu Tsuyoshi
Yoshida Shin'ichi
Lane Jack A.
Sharp Kabushiki Kaisha
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