Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
2006-07-25
2006-07-25
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
Reexamination Certificate
active
07082515
ABSTRACT:
A C element controls a pipeline register and successively transfers data packets. When a dead-lock state occurs, a data packet in the pipeline register is erased by a master reset signal, a host transfer flag operating circuit overwrites a data packet in the pipeline register so that it has a host transfer flag at the “H” level, and thereafter, when the host transfer flag is detected in the subsequent stage, the data packet is transferred to the host.
REFERENCES:
patent: 5373204 (1994-12-01), Muramatsu et al.
patent: 5404539 (1995-04-01), Onozaki
patent: 61-276033 (1986-12-01), None
patent: 03029047 (1991-02-01), None
patent: 6-83731 (1994-03-01), None
patent: 09-081540 (1997-03-01), None
Komori et al., “Multiprocessor and method of Initializing Same”, Feb. 7, 1991, English Translation of above Cited Japanese Patent No. 03029047A.
Silberschatz and Galvin. “Module 7: Deadlocks”. © 1998 http://www.csee.umbc.edu/courses/undergraduate/CMSC421/Fall99/Burt/bell-labs/mod7.1.pdf.
Rosenberg, Jerry M. “Dictionary of Computers, Information Processing & Telecommunications”. Second Edition. New York: John Wiley & Songs, Inc., © 1987. p. 239.
Arakawa Kazuya
Muramatsu Tsuyoshi
Takase Motoki
Birch,Stewart,Kolasch & Birch LLP
Chan Eddie
Li Aimee J.
Sharp Kabushiki Kaisha
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