Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
Reexamination Certificate
2001-05-02
2004-11-23
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Data flow based system
C712S025000
Reexamination Certificate
active
06823443
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data driven type information processing apparatus and to a method of controlling execution thereof. More specifically, the present invention relates to a data driven type information processing apparatus and the method of controlling execution thereof, in which transfer rate of a self-synchronous control circuit in a router as a relay apparatus on a communication network is made different from the rate of the data driven type information processing apparatus.
2. Description of the Background Art
In a data driven type information processing apparatus (hereinafter referred to as a data driven type processor), a process proceeds in accordance with the rule that when input data necessary for executing a certain process are all prepared, and resources including an arithmetic processor necessary for that process are allocated, the process is executed. A data processing apparatus including information processing operation of the data driven type uses a data transmitting apparatus employing asynchronous handshake method. In such a data transmitting apparatus, a plurality of data transmission paths are connected, and the data transmission paths transmit/receive data transmission request signals (hereinafter referred to as SEND signals) and transfer acknowledge signals (hereinafter referred to as ACK signals) indicating whether data transfer is permitted or not, with each other, whereby autonomous data transfer is performed.
FIG. 6
represents a data packet format applied to the prior art and to the present invention. Referring to
FIG. 6
, a data packet includes a destination node number field F
1
storing a destination node number ND#; a generation number field F
2
storing a generation number GN#; an instruction code field F
3
storing an instruction code OPC; and a data field F
4
storing data DATA. The generation number is a number for distinguishing data groups to be processed in parallel from each other. The destination node number is a number for distinguishing input data of the same generation from each other. The instruction code is for executing an instruction stored in an instruction decoder.
FIG. 7
is a block diagram showing a configuration of the data transmission path. The data transmission path includes a self-synchronous type transfer control circuit (hereinafter referred to as a C element)
1
a
, and a data holding circuit (hereinafter referred to as a pipeline register)
1
b
including a D type flip-flop. The C element
1
a
has a pulse input terminal CI receiving a pulse; a transfer acknowledge output terminal RO outputting a transfer acknowledge signal indicating permission or inhibition of transfer; a pulse output terminal CO outputting a pulse; a transfer acknowledge input terminal RI receiving the transfer acknowledge signal indicating permission or inhibition of transfer; and a pulse output terminal CP for providing a clock pulse controlling data holding operation of pipeline register
1
b.
FIGS. 8A
to
8
E are timing charts representing the operation of the C element shown in FIG.
7
. The C element
1
a
receives a pulse shown in
FIG. 8A
from terminal CI, and when the input transfer acknowledging signal such as shown in
FIG. 8E
provided from terminal RI represents a transfer permitted state, it outputs a pulse shown in
FIG. 8D
from terminal CO, and outputs a pulse shown in
FIG. 8C
to pipeline register
1
b
. In response to the pulse applied from C element
1
a
, pipeline register
1
b
holds the applied input packet data, or provides the held data as an output packet data.
FIG. 9
is a block diagram showing the data transmission path shown in
FIG. 7
connected sequentially through a prescribed logic circuit. Referring to
FIG. 9
, an input packet data is transferred in the order of pipeline registers
3
a
→
3
b
→
3
c
, while sequentially processed by logic circuits
3
d
and
3
e
. When pipeline register
3
a
is in a data holding state, for example, and the succeeding pipeline register
3
b
is in the data holding state, data is not transmitted from pipeline register
3
a
to pipeline register
3
b.
When the succeeding pipeline register
3
b
is in a state not holding data, or when it enters a state not holding data, the data is transmitted from pipeline register
3
a
, processed by logic circuit
3
d
and fed to pipeline register
3
b
with at least a preset delay time. Such a control in which data is transferred asynchronously with at least a preset delay time, in accordance with the SEND signal input/output at CI and CO terminals and ACK signals input/output at RI and RO terminals between adjacent connected pipeline registers is referred to as a self-synchronous transfer control, and a circuit controlling such a data transfer is referred to as a self-synchronous transfer control circuit.
FIG. 10
is a specific circuit diagram of the C element shown in FIG.
7
. The C element is described, for example, in U.S. Pat. No. 5,373,204. Referring to
FIG. 10
, pulse input terminal CI receives a pulse-shaped SEND signal (transfer request signal) from a preceding stage, and a transfer acknowledge output terminal RO provides the ACK signal (transfer acknowledge signal) to the preceding stage. Pulse output terminal CO provides the pulse-shaped SEND signal to a succeeding stage, and the transfer acknowledge input terminal RI receives the ACK signal from the succeeding stage.
A master reset input terminal MR receives a master reset signal. When a pulse at the “H” (high) level is applied to master reset input terminal MR, it is inverted by an inverter
4
e
, flip-flops
4
a
and
4
b
are reset, and the C element is initialized. Pulse output terminal CO and transfer acknowledge output terminal RO both output the “H” level signals as the initial state. That the output of transfer acknowledge output terminal RO is at the “H” level indicates the transfer permitted state, whereas the output being at the “L” level indicates a transfer inhibited state. The output of pulse output terminal CO being the “H” level represents a state in which data transfer from the succeeding stage is not requested, while the output being at the “L” level represents a state in which data transfer is requested or data is being transferred from the succeeding stage.
When the “L” level signal is input to pulse input terminal CI, that is, when a data transfer request is issued from the preceding stage, flip-flop
4
a
is set, and provides the “H” level signal at its output Q. The “H” level signal is inverted by inverter
4
d
, whereby the “L” level signal is output from transfer acknowledge input terminal RO, inhibiting further data transfer.
After a prescribed time period, the “H” level signal is input to pulse input terminal CI, and data set from the preceding stage to the C element is completed. When, in this state, the “H” level signal is input from transfer acknowledge input terminal RI, that is, data transfer is permitted by the succeeding stage, and in addition, the “H” level signal is output from pulse output terminal CO, that is, when data is not being transferred to the succeeding stage (data transfer request is not issued to the succeeding stage), then NAND gate
4
c
is rendered active, providing the “L” level signal.
As a result, flip-flop
4
b
is reset, and flip-flop
4
b
provides the “H” level signal from pulse output terminal CP to the pipeline register through a delay element
4
g
, and provides the SEND signal at the “L” level from pulse output terminal CO to the C element of the succeeding stage through a delay element
4
f
. More specifically, data transfer request is issued to the succeeding stage. The C element of the succeeding stage, receiving the SEND signal at the “L” level, outputs the ACK signal set to the “L” level, representing transfer inhibition, from the RO terminal, so as to prevent further data transfer to the C element. The C element receives the ACK signal at the “L” level from the transfer acknowledge input terminal RI, and by this signal, flip-
Hatakeyama Kohichi
Horiyama Takashi
Muramatsu Tsuyoshi
Sharp Kabushiki Kaisha
Tsai Henry W. H.
LandOfFree
Data driven type apparatus and method with router operating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data driven type apparatus and method with router operating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data driven type apparatus and method with router operating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3288711