Data driven clock generator

Details Data driven clock generator Data driven clock generator

1988-03-30

1989-08-15

Laroche, Eugene R.

Oscillators

Phase shift type

307269, 307480, 328 63, H03B 100

Patent

active

048578681

ABSTRACT:
A data driven clock generator provides a clock having a minimum cycle for a computer processor that implements asynchronous operations. The clock generator includes a basic oscillator that provides a feedback signal as a first input to a logic gate. A data valid signal, which may be generated by a multiplexer having a plurality of test inputs, is provided as a second input to the logic gate. The logic gate produces a trigger signal for starting the oscillator. If an asynchronous operation is not complete by the end of the minimum clock cycle, the oscillator is halted to stretch the clock until a data valid signal is received. The feedback signal provided to the logic gate guarantees completion of a minimum clock cycle upon receipt of a data valid signal even if the data valid signal is unstable during the clock cycle. The data driven clock generator stretches the clock on a cycle-by-cycle basis as necessary, and the oscillator completes a minimum cycle when triggered by a data valid signal even if the signal becomes unstable during the minimum cycle.

REFERENCES:
patent: 3973222 (1976-08-01), Kucharewski
patent: 4241418 (1980-12-01), Stanley
patent: 4604582 (1986-08-01), Strenkowski
patent: 4646030 (1987-02-01), Hollister
patent: 4691121 (1987-09-01), Theus

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