Data direct ingest system

Details Data direct ingest system Data direct ingest system

1987-02-09

1990-03-06

James, Andrew J.

Boots, shoes, and leggings

375118, 370 84, 370 941, 370102, H04J 322, H04J 324, H04L 2536

Patent

active

049071866

ABSTRACT:
An electronic interface circuit and method for receiving high speed serial ata, converting the data to parallel data and multiplexing different types of data together with a temporary buffer storage utilizing a First-In-First-Out (FIFO) buffer memory and controllable output interface circuits and signals is provided. Sources of the data can be, for example, a frame synchronizer used to process high speed data from a TIROS-N satellite. The circuitry of a specific embodiment includes line receivers for receiving the data and a controllable output register and line drivers for providing the output data. The input data includes a synchronizing clock signal and control signals and three types of data. A serial to parallel data converter converts the appropriate data and controllable tri-state buffers determine the sequence of providing the data to an internal data bus connected to the input of the FIFO memory.

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