Data detecting circuit

Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal gain processing

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H04N 576

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active

057295174

ABSTRACT:
A clock extracting section generates a first clock synchronized with a reproducing signal, and a second clock with a frequency twice a frequency of the first clock. An AD converter quantizes the reproducing signal at timing of the second clock. A data classifier classifies the quantized data into two quantized data streams with a period of the first clock. Each equalizer equalizes the two quantized data streams to (1,1) and (1,2,1) partial response characteristics. Each branch metric arithmetic unit calculates a corresponding branch metric respectively. A synthesizer calculates a sum of them so as to generate a synthetic branch metric. An ACS circuit and a data decoding section Viterbi-decode data according to the synthetic branch metric. As a result, even if an SN ratio is lowered by increase in interference between codes and a noises at the time of recording at high density, an error of decoded data can be decreased.

REFERENCES:
patent: 5311523 (1994-05-01), Serizawa et al.
patent: 5341387 (1994-08-01), Nguyen
patent: 5600664 (1997-02-01), Hayashi
Viterbi Detection of Partial Response on a Magneto-Optical Recording Channel, M. Tobita et al., SPIE vol. 1663, Optical Data Storage (1992), pp. 166-173.
"A Study on PRML Detection in Magneto-Optical Recording Systems"; T. Fujiwara et al.; Spring 1993; C-474, pp. 5-104.
"Performance Estimeitiion of PRML in High Density Optical Magnetic Recording Channel"; M. Kobayashi et al.; General Meeting 1995, C-468; p. 60.
"A Study on PRML Systems in Magneto-Optical Recording"; H. Osawa et al.; General Meeting 1995, C-469; p. 61.

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