Data dependency collapsing hardware apparatus

Boots – shoes – and leggings

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G06F 738

Patent

active

050519409

ABSTRACT:
A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.

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patent: 4819155 (1989-04-01), Wulf et al.
patent: 4852040 (1989-07-01), Oota
Hwang, Kai & Faye A. Briggs, "Computer Architecture and Parallel Processing", 1984, pp. 325-328.
Wulf, Wm. A. "The WM Computer Architecture", Computer Architecture News, vol. 16, No. 1, Mar. 1988, pp. 70-84.
Hwang, Kai, Computer Arithmetic, 1979, pp. 88-100.
Jouppi, Norman P. & David W. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines", Third Intn'l. Conference on Architectural Support for Prog. Languages & Operating Sys., 1989, pp. 272-282.

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