Data demodulator carrier phase error detector

Details Data demodulator carrier phase error detector Data demodulator carrier phase error detector

1988-12-05

1989-08-22

Mis, David

Demodulators

Amplitude modulation demodulator

Having specific distortion, noise or other interference...

329 50, 329107, 329126, H03D 318, H03K 904

Patent

active

048599590

ABSTRACT:
An arrangement for producing a phase error signal representing the phase error between a received phase-modulated signal and a locally generated carrier signal. The arrangement comprises two exclusive-OR gates (4) and (5) to which the received signal q(t) and sine and cosine versions s(t) and c(t) of the carrier signal are applied. The outputs of the two gates (4) and (5) control according to their level (high or low), the up/down counts of respective up/down counters (6) and (7). These counts are latched periodically by latches (9) and (10) and the latched values are modified in 2's complementers (11) and (12) and then summed in a binary adder (13) to produce a resultant phase error signal (z).

REFERENCES:
patent: 3729684 (1973-04-01), Shuda
patent: 3971996 (1976-07-01), Motley et al.
patent: 4359692 (1982-11-01), Ryan
patent: 4555667 (1985-11-01), Cressey et al.
Lindsey & Chie, A Survey of Digital Phase-Locked Loops, Proceedings of the IEEE, vol. 69, No. 4, Apr. 1981.

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