Data demodulation apparatus

Details Data demodulation apparatus Data demodulation apparatus

1997-04-21

1998-07-07

Mis, David

Demodulators

Phase shift keying or quadrature amplitude demodulator

329310, 375324, 375329, 375342, 375350, H03D 300, H04L 2722

Patent

active

057775117

ABSTRACT:
A digital modulating signal, which is a binary conversion of an RDS signal by a comparator, is sampled by a D-FF with a regeneration clock synchronized with a carrier regenerated by a carrier regeneration circuit. Next, a comparator output is input by an edge detection circuit where a data edge is detected, and the edge interval between this edge and the sampling timing edge of the regeneration clock is detected by a reliability judgment circuit where the edge interval is encoded and output as reliability data. Then, the reliability data is added as LSB data to various sampling data, and data for various symbols is regenerated at the data regeneration circuit. This minimizes the influence of the error data on the data regeneration circuit even if data is sampled erroneously.

REFERENCES:
patent: 5243299 (1993-09-01), Marchetto et al.
patent: 5436591 (1995-07-01), Henze

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