Data demodulation apparatus

Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal gain processing

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Details

360 51, G11B 2010, G11B 509

Patent

active

046882057

ABSTRACT:
A data demodulation apparatus comprises an optical head for reading out code data from a recording medium, the code data having been modulated according to the timing of a clock pulse of a predetermined frequency and recorded in the recording medium, a reproduction pulse generating PLL circuit supplied with the clock pulse and the code data, and for generating a reproduction pulse synchronized in phase and frequency with the clock pulse in a first mode, and a reproduction pulse synchronized in phase with the code data in a second mode, and means for demodulating the code data according to the timing of the reproduction pulse. The frequency of the reproduction pulse is detected by a detector circuit. The frequency of the reproduction pulse is compared with that of the clock pulse. When a difference between both frequencies is within a tolerable range, the PLL circuit is set in the second mode. When a difference between both frequencies is not within the tolerable range, it is set in the first mode.

REFERENCES:
patent: 4495474 (1985-01-01), Nishikawa et al.
patent: 4611319 (1986-09-01), Naito
Floyd M. Gardner, Ph.d., "Phaselock Techniques", 2. Aufl., New York, Chichester, Brisbane, Toronto, 1979, John Wiley & Sons, S. 84-87, 166-169.

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