Data delay/memory circuit

Details Data delay/memory circuit Data delay/memory circuit

1988-04-29

1989-01-31

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Byte or page addressing

377 79, 365194, 365 78, G11C 800, G11C 700, G11C 1900

Patent

active

048021369

ABSTRACT:
A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters. The data delay/memory circuit also includes a clock generator for supplying the clocked inverters with clock signals. These clock signals have individual clocking phases and are sequentially generated such that the clocking phase for a final stage of the data latch circuits is ahead of that for an initial stage thereof.

REFERENCES:
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patent: 3953837 (1976-04-01), Cheek, Jr.
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patent: 4353057 (1982-10-01), Bernet et al.
patent: 4613773 (1986-09-01), Koike
IBM Technical Disclosure Bulletin, vol. 12, No. 12, May 1970, pp. 2144-2145, "Complementary FET Shift Register Using a Single Phase Line", by Gaemssler.
The Electronic Engineer, Mar. 1970, pp. 59-61, "MOS Shift Registers", by George Landers.
Patent Abstracts of Japan, vol. 8, No. 248 (P-313) [1685], Nov. 14, 1984 concerning Japanese Patent Document No. 59-119594 (Kimura).

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