Data delay circuit and clock extraction circuit using the same

Details Data delay circuit and clock extraction circuit using the same Data delay circuit and clock extraction circuit using the same

1991-02-28

1991-11-19

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307608, H03K 513, H03K 5159

Patent

active

050668773

ABSTRACT:
A data delay circuit includes a first transistor, and a second transistor having a base, an emitter and a collector. Input data is applied to the bases of the first and second transistors. A constant-current source is coupled between the emitters of the first and second transistors and a negative power source. A capacitor is connected between the collector of the first transistor and the collector of the second transistor. The data delay circuit further includes a third transistor and a fourth transistor. The emitters of the third and fourth transistors are connected to the collectors of the first and second transistors, respectively. The bases of the third and fourth transistors are provided with control data having a polarity opposite to that of the input data and having an adjusted amplitude level corresponding to a desired delay time to be given the input data. First and second load resistors are respectively coupled to the collectors of the third and fourth transistors through a positive power source. Delayed input data is drawn from the collectors of the third and fourth transistors.

REFERENCES:
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patent: 4687998 (1987-08-01), Takatori et al.
patent: 4691120 (1987-09-01), Kondo
patent: 4874966 (1989-10-01), Gehrt et al.
patent: 4893036 (1990-01-01), Hester et al.
IBM Technical Disclosure Bulletin, vol. 16, No. 11, Apr. 1974, pp. 3498-3500, New York.
IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, pp. 1183-1186, Armonk, New York.

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