Data decoding circuit including phase-locked loop timing

Details Data decoding circuit including phase-locked loop timing Data decoding circuit including phase-locked loop timing

1987-10-30

1990-03-13

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

375 95, 329311, 331 1A, H03D 324

Patent

active

049088416

ABSTRACT:
A data decoding circuit which receives an input signal comprising a sequence of pulses and generates a digital data output signal and timing signals in response thereto. The circuit includes a phase-locked loop which generates timing signals in response to the input signal and an offset signal from a data separator circuit. The data separator circuit generates the digital data output signal and the offset signal, which measures the degree of correlation between the input signal as received by the data separator and the timing signal from the phase-locked loop, thereby obviating the need to match the data separator circuit closely to the phase-locked loop.

REFERENCES:
patent: 4737866 (1988-04-01), Ebata
patent: 4750193 (1988-06-01), Bailey
"Clock Recovery Phase-Locked Loop", IBM Technical Disclosure Bulletin, vol. 29, No. 10 (Mar., 1987), pp. 4427-4428.
W. C. Lindsey, et al., "Telecommunication Systems Engineering", Prentice-Hall, 1973) pp. 442-443 and 458-459.

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