Coded data generation or conversion – Digital code to digital code converters – With error detection or correction
Reexamination Certificate
2000-05-26
2002-04-16
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
With error detection or correction
C714S795000, C375S341000
Reexamination Certificate
active
06373413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a maximum likelihood decoding technique which, for example, is suitable for application to a videotape recorder or optical disk device.
2. Description of the Related Art
In the prior art, in videotape recorders and optical disk devices, digital signals which are recorded at high density are faithfully reproduced by processing reproduced signals by Viterbi decoding.
In Viterbi decoding, input data is processed by defining n types of state, determined by intercode interference, by a combination of immediately preceding input data, and updating these n types of state to the following n types of state each time the input data changes. Specifically, if the intercode interference length is m, these n states are determined by the immediately preceding m-1 bits, e.g., if the input data is logic 1 or logic 0 serial data, there are n=2
(m-1)
states.
Concerning the n states so defined, assuming that the noise contained in the reproduced signal is a Gaussian distribution and taking the value of the reproduced signal corresponding to each state when there is no noise present as a reference amplitude value, the likelihood or probability of making a transition to each state is a value obtained by raising the difference between the reference amplitude value and the actual reproduced signal to a power of two (which is the distance from the reference amplitude value), and summing this square value until there is a transition to each state. In this way, in Viterbi decoding, sums are calculated respectively for paths via which transitions from the immediately preceding n states to the following states are possible, and assuming that transitions occur for paths which have the highest likelihood (smallest sum value) from the calculated results, the n states are updated to the following n states, and the history and likelihood of the identification values in each state are also updated.
By successively detecting the most likely state transitions in this way, the history up to plural preceding bits are merged into one history at a predetermined stage, and the identification result up to that time is thereby specified. This is how Viterbi decoding identifies a reproduced signal.
In Viterbi decoding which processes reproduced signals in this way, if the noise superimposed on the reproduced signal is random noise, maximum use is made of the signal power of the reproduced signal to identify the reproduced signal, and this permits improvement of the error rate as compared with the decoding method where the reproduced signal is decoded by comparing it with a predetermined threshold value for each bit.
FIG. 14
is a table showing state transitions in an EPR (Extended Partial Response) 4 equalization for a recorded signal which allows a logic level inversion for one clock interval in a continuous serial bit sequence, i.e., for a recorded signal wherein d is not limited. The EPR4 is PR(1, 1, −1, −1), and intercede interference occurs up to three bits later relative to one input data.
Therefore in this combination, the state transition (output) due to the following input data is uniquely determined by the history of input data up to three previous bits. Herein, a[k] represents the input data, and a[k−1], a[k−2], a[k−3] are respectively input data one clock, two clocks and three clocks prior to the input data a[k]. A state b[k−1] due to this input data a[k−1], a[k−2], a[k−3] is shown by the values of a code S and the input data a[k−1], a[k−2], a[k−3]. In this case, in a state (S
000
) for example, if an input a[k] of value 0 is input, an output c[k] of value 0 is obtained, and the state b[k] changes to (S
000
).
In this case, as there is no limit d=1, 8 states (S
000
)-(S
111
) are obtained corresponding to combinations of three successive input data, and the output signal c[k] has five reference amplitude values −2, −1, 0, 1, 2. If these relations are represented by a trellis diagram, they appear as shown in FIG.
15
.
In this case, in Viterbi decoding, from a trellis diagram drawn by repeating
FIG. 15
, the branch metric of the difference between the reproduced signal and the reference amplitude value is summed, and the path having the least value of this sum is selected to decode the input signal.
FIG. 16
is a block diagram showing a reproduction device to which this type of Viterbi decoder is applied. In a reproduction device
1
, a reproduction equalizer
2
performs Nyquist equalization and outputs a reproduction signal RF to permit reproduction of a clock by the reproduction signal RF. A binarizing circuit
3
binarizes the equalized signal output by this reproduction equalizer
2
so as to output a binarized signal S
2
.
A PLL circuit
4
which operates based on this binarized signal S
2
as a reference, reproduces and outputs a clock CK from the reproduction signal RF. An analog/digital (A/D) conversion circuit
5
sequentially performs analog/digital conversion on the reproduction signal RF based on this clock CK, and outputs a digital reproduced signal. By performing computational processing on this digital reproduced signal, a reproduction equalizer
6
generates and outputs an EPR4 equalized signal, for example, and a Viterbi decoder
7
processes the EPR4 equalized signal from this reproduction equalizer
6
to output a binary decoded output D
1
which is a recorded signal recorded on a recording medium. Hence, this reproduction device
1
uses the technique of PRML (Partial Response Maximum Likelihood) to reproduce the binary decoded output D
1
.
FIG. 17
is a block diagram showing this Viterbi decoder
7
. In this Viterbi decoder
7
, a branch metric calculator
7
A receives a digital reproduction signal DRF due to the EPR4 equalized signal, and by performing the following computational processing on each sample value of the digital reproduction signal DRF, calculates and outputs branch metrics BM
0
[k]-BM
4
[k] relative to reference amplitude values. Herein, the branch metrics BM
0
[k]-BM
4
[k] are differences between values of the reproduced signal corresponding to each state when no noise is present (reference amplitude values which in this case are the five values 2, 1, 0, −1, −2) and a real reproduced signal level Z[k] raised to the power of 2, and are Euclidian distances of the reproduced signal level relative to the reference amplitude values.
BM
0
[k]=(Z[k]−2)
2
BM
1
[k]=(Z[k]−1)
2
BM
2
[k]=(Z[k])
2
BM
3
[k]=(Z[k]+1)
2
BM
4
[k]=(Z[k]+2)
2
(1)
Specifically, the branch metric calculator
7
A comprises plural subtractor circuits which compute the reference amplitude values from the digital reproduction signal DRF, and plural multiplier circuits which raise the subtraction results to the power of 2.
A branch metric processing circuit
7
B performs the computations of the following equations respectively in metric calculators
7
BA-
7
BH using the branch metrics BM
0
[k]-BM
4
[k] output by the branch metric calculator
7
A, and thereby calculates the metrics (S
000
, k)-(S
111
, k) which are sum values of the branch metrics input to each state. Herein, min{a, b} is processing which selects the least value of a, b.
L(S
000
, k)=min {1(S
000
, k−1)+BM
2
[k], (S
100
, k−1)+BM
3
[k]} (2-1)
L(S
001
, k)=min {1(S
000
, k−1)+BM
1
[k], (S
100
, k−1)+BM
2
[k]} (2-2)
L(S
010
, k)=min {1(S
001
, k−1)+BM
1
[k], (S
101
, k−1)+BM
2
&
Frommer William S.
Frommer & Lawrence & Haug LLP
Jeanpierre Peguy
Sony Corporation
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