Data decoding apparatus

Details Data decoding apparatus Data decoding apparatus

1998-02-13

1999-12-21

Young, B. K

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341111, H03M 112

Patent

active

060055073

ABSTRACT:
A reproduced signal from a recording medium 1 is equalized at partial response (1, 0, -1) by a reproducing equalizer 3, and is converted into a reproduced and equalized signal. A clock reproducing circuit 4 issues a reproduced clock synchronized with the timing of data identification, and applies it to a phase adjusting circuit 5. A phase control signal generating circuit 6A detects a specific pattern from a reproduced digital signal issued from an A/D converter 7, and the advance or delay amount of phase of the reproduced clock is detected by the amplitude or distribution of the sampling value. This phase deviation amount is given to the phase adjusting circuit 5 as a phase control signal. The phase adjusting circuit 5 given a delayed clock to the A/D converter 7, and controls to A/D convert the reproduced signal at correct timing.

REFERENCES:
patent: 5287025 (1994-02-01), Nishimichi
patent: 5808573 (1998-09-01), Shih et al.
European Search Report for EP 98 30 1101 dated Mar. 9, 1999.
F. Dolivo et al., "Fast Timing Recovery for Partial-Response Signaling Systems", IEEE International Conference on Communications, BOSTONICC/89, Jun. 1989, pp. 18.5.1-18.5.5.

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