Coded data generation or conversion – Digital code to digital code converters – To or from run length limited codes
Reexamination Certificate
1999-09-08
2001-05-08
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from run length limited codes
Reexamination Certificate
active
06229459
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data converting method and apparatus therefor suitable for converting digital data into a bit stream to be recorded on a recording medium in an apparatus of recording/ reproducing digital data using a recording medium such as an optical disk.
To record digital data on a recording medium such as an optical disk, a recording bit stream is demanded various characteristics. The recording bit stream is a bit pattern corresponding to a recording pattern on the recording medium. The recording bit stream is recorded as land and groove pits on the reflecting surface of a read-only optical disk, as marks in different magnetized states on a recordable optical disk such as a magneto-optical disk, and as marks having different optical constants on a phase change optical disk.
Digital data (original data) to be recorded must be converted into an optimum recording bit stream by a data conversion process in consideration of the manufacturing process of an optical disk, the optical characteristics of an optical head for reading a recording bit stream by a laser beam, and the characteristics of a signal process system for reconstructing a reproduced signal obtained by reading a recording bit stream from an optical disk into original digital data.
The read-only optical disk on which data is recorded as pits desirably has a large minimum pit length because a small minimum pit length leads to abrupt decrease in a reproduced signal output owing to deterioration of optical characteristics. To the contrary, a large maximum pit length decreases the reverse count of a reproduced signal. As a result, the clock timing reproduction performance deteriorates to increase jitter, and code errors readily occur. Therefore, the maximum pit length is desirably small.
Also, the DC and low-frequency components of a recording bit stream recorded as pits on an optical disk must be small. The DC and low-frequency components may influence tracking servo for accurately tracing a track formed on an optical disk, so they must be suppressed to accurately read a recording data stream.
Further, the width of a detection window must also be large. When original data is recorded by division into many bits, even if the pit length conditions are satisfied, the time phase margin decreases upon detection, and the reproduction clock frequency increases. As the reproduction clock frequency increases, the signal processor circuit must operate at a high speed, resulting in high circuit cost.
An example of data conversion systems considering these conditions is 8/14 conversion disclosed in Jpn. Pat. Appln. KOKAI Publication No. 6-284015 (to be referred to as reference [1]). 8/14 conversion is a data conversion system of converting 8-bit data into a 14-bit code. The code obtained by this conversion is converted into a recording bit stream such as an NRZI (Non Return to Zero-Inverse) pattern, and recorded on a recording medium. In reference [1], a table used for code conversion from 8 bits to 14 bits is optimally switched to decrease the value (DSV (Digital Sum Variation)) obtained by cumulating bits “0” and “1” of the recording bit stream as “−1” and “+1”. Thus, 8/14 conversion can satisfactorily suppress the DC and low-frequency components of the recording bit stream.
However, in reference [1], since the number of bits increases to 14/8 the original data after data conversion, the width of the detection window decreases, and the clock frequency increases at the same ratio.
In recent years, a higher data transfer speed is required of digital recording apparatuses such as an optical disk apparatus. A higher data transfer speed increases the clock frequency, which requires a high-cost signal processor circuit capable of operating at a high speed.
Jpn. Pat. Appln. KOKAI Publication No. 56-149152 (to be referred to as reference [2]) discloses another data conversion system. The data conversion system disclosed in reference [2] converts original data into a code 1.5 times in the number of bits. Since the obtained code has a run of 1 to 7 bits “0” between bits “1”, this data conversion system is generally called (1,7) RLL (Run Length Limited) coding. The data conversion system can be realized by a relatively low clock frequency and small-size circuit. However, this system does not manage DSV, unlike 8/14 conversion described in reference [1], so the DC and low-frequency components of the recording bit stream are not suppressed. In the system of reference [2], the tracking performance may deteriorate.
To suppress the DC and low-frequency components of a recording bit stream, an adjustment bit for decreasing DSV is inserted in the bit stream separately from data bits to be recorded. Inserting the adjustment bit decreases the effective capacity of the recording medium. The code obtained by reference [2] is of a variable length coding type in which conversion from 2 bits into 3 bits and conversion from 4 bits into 6 bits exist. For this reason, bit errors readily propagate.
As described above, in the conventional data conversion system, if the DC and low-frequency components of a recording bit steam are suppressed to stabilize tracking servo, the clock frequency increases undesirably for the signal processor circuit. If the clock frequency is suppressed low, the DC and low-frequency components of the recording bit steam cannot be suppressed. If the adjustment bit is inserted, the effective recording capacity of the recording medium decreases.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data converting method and apparatus therefor capable of converting input data into an output bit stream of codes with a different number of bits from that of the input data while suppressing the DC and low-frequency components of the output bit stream without increasing the clock frequency so high and inserting any redundant adjustment bit in the output bit stream.
The present invention provides A data converting method comprising the steps of converting m-bit input data into an n-bit converted code using a first table having a conversion code group in which the number of consecutive bits “0” between bits “1” of the conversion code is limited to not less than d and not more than k, the number of consecutive bits “0” on a start side of the conversion code is limited to not more than k1, and the number of consecutive bits “0” on an end side of the conversion code is limited to not more than k2; adaptively inverting a last bit of the converted code obtained in the step of converting m-bit input data; converting the converted code, which is obtained in the step of converting m-bit input data and the step of inverting a last bit, into an NRZI pattern in which an output is inverted for a bit “1” of the code and held for a bit “0” thereof; cumulating bits “0” and “1” of the NRZI pattern as “−1” and “+1”, respectively, thereby obtaining a cumulated value; and performing one of following steps (a), (b) and (c) for a current code in which the number of consecutive bits “0” on the end side of the converted code is larger than (k−k1) among converted codes obtained in the step of converting m-bit input data,
(a) executing the step of inverting a last bit, when a sum of the number of consecutive bits “0” on the end side of the current code and the number of consecutive bits “0” on the start side of a next code following the current code exceeds k,
(b) inhibiting execution of the step of inverting a last bit, when the number of consecutive bits “0” on the start side of the next code is smaller than d, and
(c) determining, as invertible positions, at least some last bits of the converted code obtained in the step of converting m-bit input data, and controlling execution
onexecution of the step of inverting a last bit at each invertible position so as to decrease an absolute value of the cumulated value at a next invertible position, when neither condition in the step (a)
Kabushiki Kaisha Toshiba
Pillsbury & Winthrop LLP
Young Brian
LandOfFree
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