Data converter with vertical resistor meander

Details Data converter with vertical resistor meander Data converter with vertical resistor meander

2000-12-18

2002-04-09

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S154000

Reexamination Certificate

active

06369736

ABSTRACT:

BACKGROUND OF THE INVENTION
The present embodiments relate to data converters, and are more particularly directed to converters using resistor strings.
Data converters may be used in various types of electronic circuits, or may be formed as a single integrated circuit device. Such converters typically take one of two forms, either as a digital-to-analog converter (“DAC”) or an analog-to-digital converter (“ADC”). For the DAC, its operation converts an input digital signal to an output analog signal, typically where the amplitude of the output analog signal corresponds directly to the magnitude of the input digital signal. Conversely, the ADC converts an input analog signal to an output digital signal, typically where the value of the output digital signal corresponds directly to the amplitude of the input analog signal. In many configurations, both DACs and ADCs implement a resistor string that includes a number of series-connected resistors, where each resistor provides a voltage tap at each of its ends. Typically, the overall string is biased at opposing ends by two different reference voltages, where for example one such voltage is a positive voltage and the other is ground. Also in this regard, in an effort to maintain the linearity between the digital input and the analog output, a common concern in the art is to endeavor to ensure that each resistor in the string has as close to the same resistance value as all other resistors in the string. Accordingly, the resistor string forms a series voltage dividing network and each of the voltage taps is accessible as part of the operation for the data conversion (i.e., either from digital to analog, or analog to digital).
For further background to converters and by way of example,
FIG. 1
illustrates a typical configuration of a prior art DAC
10
, and is detailed briefly below. In addition, since the primary focus of the preferred embodiments described later is directed to resistor strings as used in either a DAC or an ADC, the following discussion provides one example of such a string as used in a DAC, but is not unduly lengthened by also providing a detailed analysis of an ADC. Instead, such an understanding is left to one skilled in the art.
FIG. 1
illustrates a typical configuration of a prior art DAC
10
, and is detailed briefly here with additional detail ascertainable by one skilled in the art. By way of example and as appreciated later, DAC
10
is a 4-input 16-output DAC, while numerous other dimensions may exist for different DAC configurations. In general and as detailed below, DAC
10
is operable to receive a 4-bit input word, designated from least significant bit to most significant bit as I
0
-I
3
, and in response to the magnitude of that input to output a corresponding analog voltage. Before detailing this operation, it is first instructive to examine the devices and connections of DAC
10
. In this regard, DAC
10
includes a series-connected resistor string designated generally at
12
, and which forms a meander in that it serpentines back and forth. Additionally, DAC
10
is generally an array in nature, having a number of bit lines in the vertical dimension and a number of word lines in the horizontal dimension, and with repeated device patterns thereby forming cells in the array. Since the example of DAC
10
presents a 4-input 16-output DAC, the array of DAC
10
includes four bit lines BL
0
through BL
3
, and four word lines WL
0
through WL
3
. Also for the current example of a 4-to-16 DAC, resistor string
12
includes fifteen resistive elements R
0
through R
14
formed in the horizontal dimension. Resistive elements R
0
through R
14
may be formed using various techniques as discussed in greater detail later, where regardless of the technique used to form the resistive elements ideally each resistive element has as close to the same resistance value as all other resistors in the string. Moreover, a voltage source V
REF1
is applied across resistor string
12
, and may be of any suitable biasing voltage, which for current applications is typically on the order of 2.0 volts. For DAC
10
, string
12
is biased between V
REF1
and ground, but it should be understood that in other configurations two different non-ground potentials may be connected at opposing ends of string
12
. When ground is connected to one end of the string, it is easily appreciated that this difference of the potentials at the ends of the string equals V
REF1
. In any event, given the equal resistance of each element in the string, V
REF1
is uniformly divided across the resistive elements of string
12
.
Looking to the detailed connections with respect to resistive elements R
0
through R
14
, each resistive element provides two taps from which a voltage may be measured as detailed below. For example, looking to resistive element R
0
, it provides a tap T
0
and a tap T
1
, while resistive element R
1
shares the same tap T
1
and provides another tap T
2
, and so forth. Each tap has a switching device connected between it and a corresponding output bit line. In the current example, each of these switching devices is an n-channel field effect transistor, and is labeled for convenience by combining the abbreviation ST (i.e., switching transistor) with the same numeric identifier corresponding to the tap to which a source/drain of the transistor is connected. For example, a source/drain of transistor ST
0
is connected to tap T
0
, a source/drain of transistor ST
1
is connected to tap T
1
, and so forth. Further, the switching transistors are arranged so that a like number of taps are coupled via corresponding switching transistors to a corresponding one of the bit lines. In the current example of DAC
10
, four taps are coupled in this manner to a corresponding bit line. For example, taps T
0
through T
3
are coupled, via corresponding switching transistors ST
0
through ST
3
, to bit line BL
0
. As another example, taps T
4
through T
7
are coupled, via corresponding switching transistors ST
4
through ST
7
, to bit line BL
1
. Each bit line BL
0
through BL
3
is coupled via a respective column access transistor, CAT
0
through CAT
3
, to a column decoder
14
. More particularly and for reasons evident below, column decoder
14
is coupled to receive the two most significant bits (MSBs) of the 4-bit word input to DAC
10
, and in response column decoder
14
controls the gates of column access transistors CAT
0
through CAT
3
. Lastly, it should be understood that column decoder
14
operates in response to an overall system supply voltage V
S1
which in the prior art is typically on the order of 5.0 volts.
Returning now to switching transistors ST
0
through ST
15
, and given the array nature of DAC
10
, it is further appreciated that the switching transistors are arranged so that a like number of switching transistors are controlled, via connection to their gates, by a corresponding word line which is further connected to row decoder
16
. Like column decoder
14
, row decoder
16
is also responsive to the system supply voltage V
S1
. Returning to the connectivity between row decoder
16
and the switching transistors, and given the current example of DAC
10
, the gates of four switching transistors are coupled to each corresponding word line. For example, the gates of switching transistors ST
0
, ST
7
, ST
8
, and ST
15
are coupled to word line WL
0
. As another example, the gates of switching transistors ST
1
, ST
6
, ST
9
, and ST
14
are coupled to word line WL
1
. Lastly in this regard, and for reasons evident below, row decoder
16
is coupled to receive the two least significant bits (LSBs) of the 4-bit word input to DAC
10
(i.e., bits I
1
and I
0
), and is also controlled in response to the least significant bit (“lsb”), I
2
, of the two MSBs input to column decoder
14
. More particularly, each least significant bit I
0
and I
1
is coupled as an input to a corresponding exclusive OR gate EOG
0
and EOG
1
as a first input, while the second input of exclusive OR gates EOG
0
and EOG
1
is connected to re

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