Coded data generation or conversion – Converter compensation
Reexamination Certificate
2002-03-28
2003-11-04
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S155000
Reexamination Certificate
active
06642866
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a data converter, and more particularly, an analog to digital data converter using active interpolation to realize background auto-zeroing.
2. Description of the prior art
Using digital signals for information transmitting, processing and storing is an important foundation of the information industry. A digital signal is basically composed of a high state and a low state, so the digital signal has a high noise tolerance. In addition, the digital signals can be processed in a modular design. Therefore, circuits for transmitting, processing, and storing digital signals are key issues in the information industry.
All signals are essentially analog signals that vary continuously, such as human voices, natural light, and so on. A data converter, which can convert analog data to digital, is needed for processing analog signals into digital form. Digital signals are really continuous analog signals. In a digital signal, while the waveform of the signal varies, for instance from a high state to a low state, a transient state exists. The transient state comprises a rising edge and a falling edge. Thus, the waveform of the digital signal is not a perfect square wave. Digital signals are less ideal when the digital signals are frequently switched between different states. For processing the non-ideal digital signals, an analog to digital data converter is needed to obtain digital signals with more ideal characteristics. For this purpose, data converters must operate rapidly and continuously to obtain high frequency digital signals in real time.
Please refer to
FIG. 1
of a schematic diagram of a prior flash data converter
10
, which is used to convert an analog input signal Vin to a corresponding digital signal. The data converter
10
comprises a voltage dividing circuit
12
, an encoding circuit
16
, and a plurality of comparison units
14
. In
FIG. 1
, eight comparison units are shown for instance. The voltage dividing circuit
12
comprises a plurality of resistors such as Ra, Rb, and Rc for dividing a voltage Vdc into different reference voltages Vr
1
to Vr
8
respectively at each node. Each of the comparison units
14
comprises an amplifier
18
and a latch circuit
19
. The amplifier
18
receives the reference voltage generated by the voltage dividing circuit
12
, and an input signal Vin for amplifying the difference between these two input signals to generate a corresponding signal to the latch circuit
19
. The latch circuit
19
is triggered by a clock vclock to convert the output signal of the amplifier
18
to a digital signal in a high or low state. This converted digital signal is output to the encoding circuit
16
. The encoding circuit
16
processes (ex. Correct) and encodes the digital signals generated by the comparison units
14
.
Please refer to
FIG. 2
of a timing diagram of the clock vclock, the input signals Vin, and the output digital signals of each comparison unit while the prior data converter
10
operates. The transverse axis in
FIG. 2
is time. When the analog input signal Vin reaches the data converter
10
, the amplifier
18
compares the input signal Vin with the corresponding reference voltage and outputs a comparison result to the latch circuit
19
. According to the comparison result and a trigger of the clock vclock, the latch circuit
19
outputs a digital signal in a high state, which is shown by
1
, or a low state, which is shown by
0
. For example, at time t
1
, if the input signal Vin is less than the reference voltages Vr
1
and Vr
2
but more than the reference voltages Vr
3
to Vr
8
, then the latch circuit
19
is triggered by the negative edge of the clock vclock (which is shown by arrows) and outputs digital signals as
0
,
0
,
1
,
1
,
1
,
1
,
1
, and
1
. In this manner, the input signal Vin at time t
1
can be converted to a digital signal (
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
). The encoding circuit
16
can encode the digital signal in advance, such as
011
.
For the purpose of converting input analog signals to digital signals correctly, each amplifier must respond to the relationship between the input signal Vin and the reference voltage correctly. In a real circuit, each comparison unit generates an offset voltage due to the non-ideal characteristics of the device. This means the comparison unit adds the offset voltage to the input signal Vin and then compares the modified input signal Vin with the reference voltage. Thus, the comparison is not performed in an ideal operation situation. Additionally, if each comparison unit has different offset voltages, the data converter
10
is affected, and converts signals incorrectly.
To adjust the offset voltage in the comparison units, an auto-zeroing process is used to solve the problem. Please refer to
FIG. 3
of a schematic diagram of a data converter
20
in the prior art. The data converter comprises a voltage dividing circuit
22
for providing reference voltages Vr
1
to Vr
4
, four comparison units
24
A to
24
D, auxiliary circuits
26
A and
26
B, and an encoding circuit
28
. The comparison units
24
A to
24
D have the same structure. The comparison unit
24
A comprises four switches SP
1
, SP
2
, SP
3
and SP
4
, a differential amplifier Ka with one output end and two input ends, a capacitor CO, and a latch circuit Ja. The switches SP
1
to SP
4
are controlled by a control signal vc
1
and an inverted signal of the control signal vc
1
, shown as {overscore (vc
1
)}. The amplifier Ka comprises a feedback circuit controlled by the switch SP
3
electrically connected to the input end P
11
and the output end P
12
. The other input end of the amplifier Ka is electrically connected to a common mode voltage V
0
. The latch circuit Ja is triggered by the clock vclock. Each comparison unit is electrically connected to a resistor Rc.
The data converter
20
operates as following. The amplifier compares the input signal Vin with the reference voltage and outputs the comparison result to the latch circuit. The latch circuit is then triggered by the clock vclock to generate a digital signal. To compensate the offset voltage generated in the amplifiers, the switches in each comparison unit conduct or open to allow each comparison unit to perform a comparing process or an auto-zeroing process alternatively. The comparison unit
24
C shown in
FIG. 3
is in the auto-zeroing process. Please notice that the switches in the comparison unit
24
C can conduct the feedback circuit of the amplifier Kc, and the capacitor can be also electrically connected to a corresponding reference voltage Vr
3
. At this time, the reference voltage Vr
3
charges the capacitor C
0
via the switch SP
2
in the comparison unit
24
C. When the feedback circuit conducts, a close loop is formed at the node P
31
so that the amplifier Kc is virtually grounded to the common mode voltage V
0
. Thus, the charge amount in the capacitor C
0
is dependent on the reference voltage Vr
3
. The charge amount is enough to compensate the offset voltage of the amplifier Kc and the purpose of auto-zeroing is achieved.
After the auto-zeroing process, each comparison unit switches to a comparing process and compares the input signal with the reference voltage. Then, a corresponding digital signal is output from the latch circuit. For example, the comparison unit
24
A shown in
FIG. 3
is performing a comparison process. Please notice that the switch SP
3
is opened so that the feedback circuit does not conduct and make the amplifier Ka in an open loop. The signal Vin is input to the capacitor C
0
via the switch SP
1
so that voltages on both terminals of the capacitor C
0
are modified. Since the charge amount of the capacitor C
0
in the auto-zeroing process corresponds to the reference voltage, the voltage on node P
11
corresponds to a comparison result between the input signal Vin and the reference voltage. This comparison result is sent to node P
12
by the amplifier Ka. Finally, the comparison result is output to the latch
Chen Kuo-Hsin
Kuo Tai-Haur
Lin Hsin-Chieh
Lin Jyh-fong
Hsu Winston
Jeanglaude Jean Bruner
VIA Technologies Inc.
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