Data control system allowing simultaneous communication between

Details Data control system allowing simultaneous communication between Data control system allowing simultaneous communication between

1986-07-16

1988-11-29

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1340, G06F 1342

Patent

active

047886420

ABSTRACT:
A bus control system for a common data bus between a central processing unit (CPU) and a plurality of peripheral devices has an address decoder which decodes address data from the CPU to output one of a chip selection signal S.sub.c and a plurality of chip selection signals S.sub.1 to S.sub.n. The chip selection signal S.sub.c brings all the devices into operative conditions simultaneously, while each of the chip selection signals S.sub.1 to S.sub.n brings a respective one of the devices into an operative condition. Each of the devices has a first register which is responsive to a corresponding one of the chip selection signals S.sub.1 to S.sub.n to store data appearing on predetermined bit-lines of the data bus and first and second gate circuits. When the CPU causes the address decoder to output the chip selection signal S.sub.c in a write mode, the first gate circuit of each device passes data appearing on the bit-line of the bus designated by the data in the first register into a second register. Thus, the CPU can write data into the second registers of all of the devices simultaneously. When the CPU causes the address decoder to output the chip selection signal S.sub.c in a read mode, the second gate circuit of each device outputs data contained in a third register onto the bit-line of the bus designated by the data in the first register. Thus, the CPU can read data from the third registers of all of the devices simultaneously.

REFERENCES:
patent: 3644901 (1972-02-01), Zingg
patent: 4079452 (1978-03-01), Larson et al.
patent: 4281392 (1981-07-01), Grants et al.

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