Data conflict prevention for processor with input/output device

Details Data conflict prevention for processor with input/output device Data conflict prevention for processor with input/output device

1986-04-10

1989-12-19

Eng, David Y.

Boots, shoes, and leggings

364240, 3642402, 3642407, 3642399, 3642281, 364247, 3642478, 3642328, G06F 1338, G06F 1340

Patent

active

048886858

ABSTRACT:
A computer and an input/output device are connected via an interface bus. The input/output device has registers. The computer and the input/output device operate upon the basis of a pair of clock signals. When the input/output device accesses the registers via read and write buses, the buses are precharged during a first period of first clock signal of the pair and controlled by data during a first period of second clock signal of the pair. When the computer accesses the registers via the interface bus, the bus is precharged during the first period of the second clock signal of the pair and controlled by data during the first period of the first clock signal of the pair.

REFERENCES:
patent: Re32163 (1986-05-01), Tokuda et al.
patent: 4164787 (1979-08-01), Aranguren
patent: 4594661 (1986-06-01), Moore et al.
patent: 4672587 (1987-06-01), Geiger et al.
IBM Technical Disclosure Bulletin, Data Buss Precharge, by J. C. Hsieh, vol. 18, No. 6, Nov. 1975.

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