Data compensation/resynchronization circuit for phase lock loops

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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Details

327159, 327292, H03L 706

Patent

active

057774986

ABSTRACT:
A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.

REFERENCES:
patent: 5307381 (1994-04-01), Ahuja
patent: 5406590 (1995-04-01), Miller et al.

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