Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reissue Patent
2000-07-07
2003-03-25
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S159000, C327S292000
Reissue Patent
active
RE038045
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to circuits that directly compensate for delays induced by clock generation logic and distributed clock drivers in phased-lock loop (PLL) applications.
Referring to
FIG. 1
, a prior art clock generation/distribution block diagram
100
is shown. External Reference Clock
102
, REF CLK, is applied to one input of Phase Detector
105
, and Frequency Divider Output Signal
155
is applied to the other input of Phase Detector
105
. When the PLL is locked, External Reference Clock
102
and Frequency Divider Output Signal
155
are the same frequency. The output of Phase Detector
105
, which is a DC voltage representing the phase difference between External Reference Clock
102
and Frequency Divider Output Signal
155
, is applied to the input of Loop Filter
110
.
Loop Filter
110
is a low pass filter with gain, and is used to set dynamic PLL characteristics. The output of Loop Filter
110
is applied to the input of Voltage Controlled Oscillator (VCO)
115
. The output of Voltage Controlled Oscillator
115
is Voltage Controlled Oscillator Output Signal
150
, a variable frequency which is a function of the Voltage Controlled Oscillator
115
input. Voltage Controlled Oscillator Output Signal
150
is applied to the input of Divide-by-N Frequency Divider
135
, that divides the frequency of Voltage Controlled Oscillator Output Signal
150
by the number N. Divide-by-N Frequency Divider
135
is programmed by Programming Input Signal
180
PROG. Frequency Divider Output Signal
155
is applied to one input of Phase Detector
105
as previously mentioned.
Voltage Controlled Oscillator Output Signal
150
is routed to a multiplicity of output clock drivers, being First Clock Driver
120
, Second Clock Driver
125
, . . . Nth Clock Driven
130
. Each clock driver outputs a distributed clock, these being First Distributed Clock Output Signal
137
, Second Distributed Clock Output Signal
140
, . . . Nth Distributed Clock Output Signal
145
, respectively. The accumulated delay of interest occurs between Voltage Controlled Oscillator Output Signal
150
and each of the distributed clocks, First Distributed Clock Output Signal
137
, Second Distributed Clock Output Signal
140
, . . . , and Nth Distributed Clock Output Signal
145
.
The detrimental effects of unwanted and uncontrolled delays on the operation of digital circuitry are well known. Because digital circuitry operation in general depends upon the timing accuracy of logic transition edges, such as the transition from logic low to logic high or from logic high to logic low, the general effect of uncontrolled digital delays is to affect either the ability of a circuit to clock on the proper transition edge due to delay accumulation or to intermittently clock on the correct edge due to variations in accumulated delay. This latter effect can also manifest itself as noise in circuits whose final performance depends upon the regularity of clock edges in order to achieve high spectral purity, as is the case in frequency synthesizers which use PLLs.
All of the common digital logic elements contain detailed timing data as part of their data sheets. This information is provided to allow the designer to make proper timing budgets or allocations for the application of signals to the various functional inputs of the logic element so as to ensure proper circuit operation. The data sheets also contain timing information relative to the internal delays of the logic element so that output signals tray be characterized in time with respect to input signals.
Large digital circuits can require special software simulation tools is order to characterize the delay safety margins and problem areas, and unless this is done overall circuit performance can become problematical at best due to unforeseen delay accumulations. The extent of the problem is increased because the delay of logic elements is typically also a function of temperature, thus unwanted accumulated delays vary with temperature.
All the foregoing are well known to the art. An additional consideration, also known to the prior art, is the increase in sensitivity to delay problems as the frequency of circuit operation increases. This is due to the fact that unwanted accumulated delays which may not be of great importance at low frequencies may become critical at higher frequencies. Since the state of the art is toward increasing frequency of operation, as in communications equipment or computer equipment, the requirements for analysis and compensation of unwanted delays continues to be relevant.
In addition to the above causes for unwanted digital delays, there also are transmission line effects which become important as the frequency of operation increases. The interconnection tracks on printed circuit boards must be considered as transmission lines at high frequencies, and require proper termination and layout for optimum performance. These transmission line effects are a source of additional unwanted delay to digital signals, and the departure from ideal transmission line performance causes distortion in digital signals which often produce changes in the timing of edges.
Undesired signal delays have been an integral part of system design considerations for years. One example of system level considerations is the effect of signal delays on the distribution of supposedly identical clocks throughout a system In this application the signal delays can be different to each drop point of a distributed clock, for example, which means that the relative timing information contained in the edges of a digital clock varies from drop point to drop point. The frequency does not change, but the accuracy of edge timing may be compromised throughout the system.
One prior art approach to resolve this situation is to overspecify the digital elements involved in the clock distribution system, so that extremely small incremental delays are achieved and the magnitude of the worst case total delay error is held within desired limits. This approach has penalties in cost, power and increased generation of electro-magnetic interference due to faster logic elements being used.
Another prior art approach is to compensate for differences in delay at drop points by inserting compensation delay in the paths with least delay, typically by inserting otherwise unneeded logic elements in series with a low delay path to increase delay. This approach has the disadvantages that cost increases, power efficiency decreases, parts count increases, the delay of individual logic elements varies from part to part and with temperature, and close matching of overall delay between distribution drop points may, in the final analysis, not be practical.
There is thus an unmet need in the art to be able to utilize a method for PLL clock distribution which does not have the disadvantage of large differences in logic signal edge timing between different drop points. Therefore, it would be advantageous in the art to be able to describe a method and structure for distributing PLL digital clock signals in which the delays between drop points are compensated by a method which has predictable performance.
SUMMARY OF THE INVENTION
The present invention discloses a circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit of the present invention contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.
According to a first embodiment of the present invention, the circuit comprises a phase detector which receives a reference clock signal and generates a voltage signal representative of a phase difference between the reference clock signal and another input signal to the phase detector; a loop filter that receives the voltage signal generated by the
Cometti Aldo Giovanni
O'Bleness R. Frank
Jorgenson Lisa K.
Lam Tuan T.
Santarelli Bryan A.
STMicroelectronics Inc.
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