Data communications circuit with multi-stage multiplexing

Details Data communications circuit with multi-stage multiplexing Data communications circuit with multi-stage multiplexing

2000-04-25

2004-01-06

Chin, Wellington (Department: 2664)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S532000

Reexamination Certificate

active

06674772

ABSTRACT:

BACKGROUND OF THE INVENTION
High-speed data communication systems commonly use multiplexing transmitters and demultiplexing receivers. In such a system, as illustrated in
FIG. 1
, transmit data arrives on a set of parallel lines
113
and is multiplexed onto the transmission line
114
. The multiplexer converts the parallel signal at the reference clock rate on lines
113
into a serial signal at the bit clock rate on line
114
. At the other end of the link, the serial signal arrives on input line
115
and is demultiplexed onto parallel outputs
116
. In such a system, the bit clock that sequences multiplexer
102
and demultiplexer
103
has a frequency that is a multiple of the reference clock
111
used to clock parallel input
113
and parallel output
116
. In the example of
FIG. 1
where the multiplexing rate is 4:1, the bit clock would be at four times the frequency of the reference clock. In actual systems, a ratio of 10:1 or 20:1 is typical.
Phase-locked loop clock multipliers have been used to multiply the frequency of the reference clock to generate the bit clock. In
FIG. 1
clock
111
is input to clock multiplier
101
which multiplies the clock frequency to generate bit clock
112
. Bit clock
112
is then used by multiplexer
102
to multiplex parallel input
113
onto the input of driver
104
which drives the multiplexed data onto output line
114
. The bit clock is also used by demultiplexer
105
to separate the multiplexed input stream on input line
115
onto parallel outputs
116
.
FIG. 2
illustrates a prior art phase-locked loop clock multiplier. The bit clock, bclk is generated by voltage-controlled oscillator
121
. This clock is then divided down to the reference clock rate by a divide-by-N counter
122
. The divided clock, dclk, is then compared to the input reference clock, rclk, by phase comparator
123
. The phase comparator signals the phase difference between rclk and dclk to the charge pump and loop filter
124
which adjusts the control voltage of the VCO to bring rclk and dclk into phase. Further details of phase-locked loops are described in Dally and Poulton,
Digital Systems Engineering
, Cambridge, 1998, pp 441-447.
An alternative prior art multiplexing data communication system that uses a multi-phase clock rather than a clock multiplier is illustrated in FIG.
3
. In the figure a four-phase clock, p
1
-p
4
, is used to multiplex parallel lines
113
onto output line
114
and to demultiplex serial input
115
onto parallel lines
116
. The four-phase clock is generated by a delay-locked loop (DLL) comprising tapped delay line
131
, phase comparator
123
, and charge pump
124
. The tapped delay line is itself composed of four delay elements
132
-
135
. Phase comparator
123
compares the output of the delay line, p
4
, with the reference clock and signals the charge pump to adjust the control voltage, vctrl, of the delay line to bring p
4
and rclk into phase. When the loop has converged, vctrl is set at a value that causes delay line
131
to have a delay of exactly one reference clock cycle. To the extent that delay elements
132
-
135
are matched, the four phases are equally spaced with one bit-time of delay between each phase. In the multiplexer, the rising edge of each phase sequences the corresponding bit onto the line, and in the demultiplexer the rising edge of each phase samples the value on the line onto the corresponding parallel output. Further details of delay-locked loops are described in Dally and Poulton,
Digital Systems Engineering
, Cambridge, 1998, pp 428-441, and details of multiplexing data communication systems using DLLs are described in pp. 537-540 and 547-548 of the same reference.
Prior art data communication systems based on PLL clock multipliers and multi-phase DLLs have large amounts of jitter due to the method used to generate timing signals. Phase-locked loop based clock multipliers have large amounts of jitter because the phase error at the end of each cycle accumulates until the control loop can respond. As described in Kim, Weigant, and Gray, “PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design,”
ISCAS
1994, pp. 31-38, this error accumulation multiplies the jitter of the basic delay elements by a factor that is inversely proportional to the loop bandwidth. For typical phase-locked loops, the jitter is multiplied by a factor of at least 10.
Communication systems based on multi-phase delay-locked loops do not accumulate jitter from cycle-to-cycle like PLL clock multipliers. However, they do introduce jitter due to cumulative phase mismatches. Due to device mismatches in the delay elements, there is a variation in the delay of each stage of the delay line. These phase mismatches accumulate over the length of the delay line leading to large jitter values, particularly when the multiplexing rate is high.
SUMMARY OF THE INVENTION
To reduce the number of precision clock signals required in a multiplexing circuit, either a multiplexer or a demultiplexer, a multiplexing circuit in a data communication circuit is formed in multiple stages. Specifically, a data communication circuit for serializing data on a communication link comprises a higher frequency data multiplexing stage and a lower frequency data multiplexing stage. The higher frequency data multiplexing stage is coupled between the communication link and an intermediate frequency signal. The lower frequency data multiplexing stage is coupled to the higher frequency data multiplexing stage between the intermediate frequency signal and the lower frequency signal. A data stream on the communication link has a first number of bitstreams, typically a single bitstream, and the intermediate frequency signal has a data stream of a second number of parallel bits greater than the first number. The lower frequency signal has a data stream of a third number of parallel bits greater than the second number. The stages are clocked by a clock signal from a common clock source, but the clock signal is more precisely distributed to the higher frequency stage.
In a data transmitter, each of the data multiplexing stages is a data multiplexer, and in a data receiver, each of the data multiplexing stages is a data demultiplexer.
In a multiplexer, a lower frequency data multiplexer multiplexes parallel bits of a lower frequency data signal to an intermediate frequency signal of parallel bits. A higher frequency data multiplexer multiplexes the bits of the intermediate frequency signal to a higher frequency signal on the communication link.
In a demultiplexer, a higher frequency data demultiplexer demultiplexes the data on the communication link to an intermediate frequency signal. A lower frequency data demultiplexer further demultiplexes the intermediate frequency signal.
Preferably, the entire multiplexing circuit is on a single chip. The common clock signal may be divided by a ring counter for application to the lower frequency stage. The preferred clock is a multiplying delay locked loop bit clock generator.
In one embodiment, the data stream on the communication link is a one-bit-wide bitstream, and the intermediate frequency signal comprises two parallel bits. In another embodiment, the second number of parallel bits is greater than 2. In the preferred implementation of that embodiment, the higher frequency data multiplexing stage is clocked by an N-phase overlapping clock. Each bit of the intermediate frequency signal is enabled in the higher frequency data multiplexing stage by concurrence of two clock phases.


REFERENCES:
patent: 5361254 (1994-11-01), Storck et al.
patent: 6114915 (2000-09-01), Huang et al.
Dally, William J. and Poulton, John W.,Digital Systems Engineering, Cambridge University Press, 1998, pp. 428-447, 537-540 and 547-548.
Kim, Weigant and Gray, “PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design,” ISCAS, 1994, pp. 31-34.
Waizman, A., “A Delay Line Loop for Frequency Synthesis of De-Skewed Clock,” IEEE International Solid-State Circuits Conference, 1994, pp. 298-299.
Dally, William J. and Poulton, Jo

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