Data communication system with hardware protocol parser and...

Details Data communication system with hardware protocol parser and... Data communication system with hardware protocol parser and...

2007-11-06

2007-11-06

Caldwell, Andrew (Department: 2142)

Electrical computers and digital processing systems: multicomput

Network-to-computer interfacing

C713S324000

Reexamination Certificate

active

10447824

ABSTRACT:
A communication processor comprises a data link layer parser circuit (310) and a plurality of network layer parser circuits (322, 326). The data link layer parser circuit (310) receives a data link layer frame, and removes a data link layer header therefrom to provide a network layer frame as an output. Each network layer parser circuit corresponds to a different network layer protocol, and is selectively activated to receive the network layer frame and to process a network layer header therefrom to provide a transport layer frame as an output. The data link layer parser circuit (310) further examines a portion of the network layer frame to determine which of the plurality of network protocols is used. The data link layer parser circuit (310) activates a corresponding one of the plurality of network layer parser circuits (322, 326) in response, while keeping another one of the plurality of network layer parser circuits (322, 326) inactive.

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