Patent
1996-02-01
1997-01-07
Kim, Ken S.
39518319, 395852, 395873, G06F 15163
Patent
active
055926282
ABSTRACT:
Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data. When a transmitting end terminates transfer of the dummy data, the sending station can guarantee the termination of cache invalidation, which is performed by the processor element serving as a receiving station to attain the consistency of the contents of preceding storage data main storage and a cache memory.
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Dewa Masami
Ikeda Masayuki
Ishizaka Ken-ichi
Kobayakawa Kazushige
Nagasawa Shigeru
Fujitsu Limited
Kim Ken S.
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