Data communication system utilizing a scalable, non-blocking, hi

Details Data communication system utilizing a scalable, non-blocking, hi Data communication system utilizing a scalable, non-blocking, hi

1997-02-13

2000-05-09

Nguyen, Chau

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370429, H04L 1256

Patent

active

060613580

ABSTRACT:
A high bandwidth central memory controller utilizing a pipelined TDM bus such that each serial interface can sustain a bandwidth of up to 100 MByte/second for both the transmission and reception of variable length frames. Each port is assigned a fixed number of queues, a TDM slot number and the address routing for all other queues associated with the remaining ports at initialization, such that when a frame is received, the appropriate queue is determined from the addressing in the frame header and the initialized route tables. When the port's TDM slot for a memory request is active, a request for the output queue is made to the central memory controller if an "output queue available" indication is returned and the frame data is placed on the bus during the input port's data TDM slot. If the output queue is not available, the input port may either discard the received data frame or generate a busy/reject frame to be placed on one of its own output queues during its TDM data slot.

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