1996-03-12
1997-06-10
Gordon, Paul P.
Excavating
371 377, H03M 1300
Patent
active
056383843
ABSTRACT:
In order to combine an ARQ system and an FEC system, an error correction code is inserted between an error detection code for a variable-length ARQ frame and a frame boundary flag pattern. Information to be transmitted is divided into blocks having a suitable length by a block divider in accordance with a line quality judged by a line quality judger, and then subjected to a framing operation by an information frame preparer. The information subjected to the framing operation is attached with a CRC code by a CRC code generation/application circuit, subjected by a zero insertion circuit to an insertion of a suitable number of zero bits therein to provide a distinguished frame boundary with a flag, and the transmitted.
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Martins, A.C. and Alves, J.C., "ARQ Protocols with Adaptive Block Size Perform Better Over a Wide Range of Bit Error Rates," IEEE Transactions on Communications, vol. 38, No. 6 (Jun. 1990), New York, pp. 737-739.
Shiozaki, A. et al., "A Hybrid ARQ Scheme with Adaptive Forward Error Correction for Satellite Communications," IEEE Transactions on Communications, vol. 39, No. 4 (Apr. 1991), New York, pp. 482-484.
Ishibashi, Y. and Iwabuchi, A., "Throughput Analysis of Adaptive ARQ Schemes", Electronics and Communications in Japan, vol. 72, No. 9 Part I (Sep. 1989), New York, pp. 14-25.
Aoki Takayasu
Hayashi Katsuhiko
Murano Katsumi
Sato Hiroaki
Tateishi Toru
Brown Thomas E.
Gordon Paul P.
Kabushiki Kaisha Toshiba
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