Data communication system

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364517, 370112, H04J 306

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active

047274956

ABSTRACT:
The 16 kbit/s HDLC formatted signalling channel for each of 256 ISDN subscribers is separated from the data channel(s) at the exchange line circuit and TMD multiplexed into a 4 Mbit/s stream provided to a common signalling handler. In the handler, a receiving element processes each new bit of the 4 Mbit/s stream with 47 bits read out of a channel parameter store by a channel number provided by a channel allocation store. The 47 bits include the previous 7 received bits and a message byte address for that channel. When those 7 bits and the new bit form a new deformatted message byte, that byte is written into an incoming message store at a location determined by the current channel number and message byte address. Using a FIFO buffer, messages are read from the incoming message store by a processor in the order in which they are completed.

REFERENCES:
patent: 4394774 (1983-07-01), Widergren et al.
patent: 4531211 (1985-07-01), Hadziomerovic
patent: 4531212 (1985-07-01), Hadziomerovi
patent: 4577314 (1986-03-01), Chu et al.
Proceedings of the International Switching Symposium, Session 31 B, Paper 6, May 7-11, 1984, Florence, IT, pp. 1-7, North-Holland; G. Taille et al: "A Laboratory Model of a Signalling Transfer Point (STP)", pp. 2-4; paragraph 3.
Proceedings of the International Switching Symposium, Session 21B, Paper 3, May 7-11, 1984, Florence, IT, pp. 1-6, North-Holland; G. Ribbeck et al: "EWSD as a Basis for ISDN", pp. 4, 5; paragraph 5.
Proceedings of the International Switching Symposium, Session 21B, Paper 2, May 7-11, 1984, Florence, IT, pp. 1-8, North-Holland; S. Giorcelli et al: "Experiment of ISDN Facilities in a Proteo UT10/3 Local Exchange", p. 2, left-hand col, lines 45-64; pp. 2, 3, paragraph 2.2; p. 7, FIG. 2.2.1.

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