Data communication link

Details Data communication link Data communication link

2006-04-18

2006-04-18

Ngo, Ricky (Department: 2663)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C375S221000

Reexamination Certificate

active

07031347

ABSTRACT:
In order to enable high speed, high bandwidth data transfer between two ASIC devices, for example in a backplane, a wide parallel input data word is divided into a smaller number of words, and each smaller word is converted to serial form and then transmitted over a respective sub-link at a high clock rate relative to the system clock. At the receiving side, the clock is recovered from the serial words, and the serial words are converted back to parallel form. An alignment process is then carried out, firstly involving detecting the positions of the bits of the words and then storing the words in a buffer FIFO register. The words are clocked out of the FIFO register in synchronism under control of the system clock once it is detected that valid words are received in the FIFO registers.

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Search Report and Examination Report for UK Application No. GB 0006291.9 corresponding to the Instant application.

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