Data communication circuit

Details Data communication circuit Data communication circuit

1994-06-20

1995-12-05

Tse, Young

Pulse or digital communications

Multilevel

With threshold level

375219, 370 32, 341 56, H04L 2534, H03M 516

Patent

active

054736358

ABSTRACT:
A data communication circuit comprising a slave device (3), a master device (2) and a two-wire bus (6) wherein the master device (2) creates a potential difference (V(t)) between the two wires so as to provide power to the slave device (3). The slave device (3) comprises a pulse decoder (20) for detecting the pulses and producing a synchronisation signal (Clk) upon the detection of each pulse. The master device (2) also comprises a pulse control circuit (40) for causing the pulse creating circuit to create a series of data pulses having the same state when the digital information is read from the slave device (3). In addition, the slave device (3) further comprises a circuit (43,58) for changing the state of selected ones of the data pulses in the series in response to the digital information to be read.

REFERENCES:
patent: 4493092 (1985-01-01), Adams
patent: 4661801 (1987-04-01), Chen et al.
patent: 4949359 (1990-08-01), Voillat
International Journal of Electronics vol. 67, No. 5, Nov. 1989, London GB pp. 809-817, XP87244 A. D. Singh "Precharged CMOS quaternary logic encoder-decoder circuits."

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