Data coherent logic for an SRAM device

Details Data coherent logic for an SRAM device Data coherent logic for an SRAM device

2002-12-17

2004-07-13

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S239000

Reexamination Certificate

active

06762973

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor memory devices, such as static random access memory (“SRAM”) devices. More particularly, the present invention relates to an SRAM device having data coherent logic for resolving timing conflicts related to reading and writing operations.
BACKGROUND OF THE INVENTION
An SRAM is a semiconductor memory device that allows data to be stored in a static manner, i.e., in a manner that does not require any refresh cycles to maintain stored data. Many SRAM devices utilize a “pipeline” system to temporarily store address and data signals prior to writing data into the SRAM array. In these types of systems, data is provided on a data bus during one clock cycle and an address is provided on the address bus during a subsequent clock cycle. Read and write operations typically use the same input/output pad, and the input and output buffers operate in a mutually exclusive manner (e.g., for the output buffer to transfer read data out of the device, the input buffer for receiving write data must be inactive, and vice versa).
In these types of memory devices, write operations take longer than read operations. This may cause problems when a write operation is immediately followed by a matching read operation (i.e., a read operation requesting data from the same address as the write operation). In conventional SRAM devices, time or clock cycles may be lost because the read operation must wait for the write operation to complete prior to reading the data from the memory location. These lost clock cycles may significantly reduce the efficiency and bandwidth of the system.
Efforts have been made to reduce and/or eliminate these problems. One such solution involves the use of buffers or shift registers within an SRAM device to hold data prior to writing the data into the SRAM array. In these types of devices, when a match occurs for the data (i.e., when the address of the data requested for a read operation is the same as the address of data that being written to the SRAM array), the matched data may be transferred from the corresponding shift register into the output register of the device by use of an output strobe signal.
However, even in these types of systems, memory conflicts occur. Because the same pad is used to input data into the SRAM device (e.g., for a write operation) and output data from the SRAM device (e.g., in response to a read operation), timing conflicts between memory operations may occur. Use of the input/output pad is controlled by the output strobe signal and a data strobe signal (which is used to validate data written to the SRAM device). The data strobe signal and the output strobe signal each has its own specific timing requirements. The output strobe signal is usually the fastest and most critical signal in an SRAM design. In contrast, the data strobe signal requirements are more relaxed and depend on other requirements, such as data setup and hold times. As a result, in certain situations, the difference in timing between the data strobe signal and the output strobe signal may result in a conflict of interest.
The present invention provides a data coherent SRAM system, which overcomes the foregoing drawbacks of prior memory systems and resolves timing conflicts related to reading and writing operations.
SUMMARY OF THE INVENTION
The present invention provides data coherent logic for an SRAM device. One embodiment the present invention utilizes a data strobe signal and an output strobe signal to control data written into and read out of the SRAM device from an input/output pad. The present invention employs logic that is designed to resolve timing conflicts between the data and output strobe signals to provide data coherence. In one embodiment, the output strobe signal is selectively delayed when a match occurs for data requested in a read cycle immediately following a write cycle, thereby allowing time for the data to be registered before being outputted from the device. The signals are optimized to reduce the time period when neither the input nor output buffer is driving the memory device.
According to a first aspect of the present invention, an SRAM system with data coherence is provided. The SRAM system includes: an SRAM array; a plurality of registers for holding data and addresses for write cycles; a data strobe line that provides a data strobe signal for selectively registering data in the plurality of registers; an output strobe line that provides an output strobe signal for selectively outputting data from the SRAM array for read cycles; and an output strobe circuit that is coupled to the output strobe line and that is adapted to selectively delay the output strobe signal in response to a first match condition, which occurs when a read cycle immediately follows a write cycle and requests data from the same address as the write cycle, the delay being effective to allow sufficient time for the data to be registered and selected.
According to a second aspect of the present invention, a method is disclosed for providing data coherence in an SRAM device. The method includes the steps of: detecting read and write cycles; storing data and addresses for write cycles in a plurality of registers; selectively registering data for the write cycles in the plurality of registers by use of a data strobe signal; selectively outputting data for read cycles by use of an output strobe signal; detecting a first match condition, which occurs when a read cycle immediately follows a write cycle and requests data from the same address as the write cycle; and selectively delaying the output strobe signal in response to the first match condition, the delay being effective to allow sufficient time for the data to be registered and selected.
The method may further include the steps of storing data within at least one latch associated with at least one data shift register; detecting a second match condition, which occurs when a read cycle follows two or more consecutive write cycles and requests the same data as a first write cycle; and selectively outputting data from the at least one latch in response to a second match condition.
The method may further include the steps of detecting a third match condition, which occurs in a case other than a read after write cycle; and selectively outputting data from one of the data shift registers in response to the third match condition.
These and other features, advantages, and objects of the invention will become apparent by reference to the following specification and by reference to the following drawings.


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patent: 6094399 (2000-07-01), Mick
patent: 6094703 (2000-07-01), Pawlowski
patent: 6205514 (2001-03-01), Pawlowski
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