Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2006-04-11
2006-04-11
Corrielus, Jean B. (Department: 2637)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C327S091000, C327S291000
Reexamination Certificate
active
07027544
ABSTRACT:
A data clock recovery circuit comprises a controllable quadrature clock oscillator operating at half the data rate of data input to said circuit, and a phase detector logic having detector inputs coupled to the data input and having a detector output coupled to a frequency control input of the quadrature clock oscillator. The data clock recovery circuit further comprises a parallel arrangement of sampling devices, in particular flip-flops each having a clock input which is coupled to the controllable quadrature clock oscillator, a data input for the data input to said circuit, and a data output coupled to the phase detector. Accurate control of the phase of recovered data is possible with the present circuit, which is easy to integrate on a limited chip area and in a low power consuming way.
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Corrielus Jean B.
Liberchuk Larry
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