Data capture circuit with series channel sampling structure

Details Data capture circuit with series channel sampling structure Data capture circuit with series channel sampling structure

2002-03-22

2003-07-22

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

Reexamination Certificate

active

06597225

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic data capture circuits, such as circuits which each include one or more flip-flops, memory cells or input latches, and more particularly to signal sampling techniques for use in such circuits.
BACKGROUND OF THE INVENTION
Data capture circuits include circuits such as flip-flops, memory cells and latches, as well as sense amplifiers and other types of comparators, and are commonly used in a wide variety of integrated circuit applications.
A problem that can arise in conventional data capture circuits relates to the manner in which signals are introduced into the circuits. For example, in the case of a sense amplifier, an input signal and its Boolean complement are typically introduced or “sampled” at corresponding complementary inputs of the sense amplifier during an initialization mode of operation. Typically, a conventional sense amplifier is configured such that these complementary input signals remain connected to the corresponding input structures of the circuit while the circuit is making its decision regarding the introduced input signals, that is, while the circuit is in an evaluation mode of operation after completion of the initialization mode. This is generally not a problem when the inputs are Boolean complements of one another. However, in situations in which the inputs are non-complementary, leaving the inputs connected during the evaluation mode can lead to an undesirable increase in the power dissipation of the circuit.
Sense amplifiers and other comparators which process non-complementary inputs are described in U.S. patent application Ser. No. 09/870,436, filed May 30, 2001 in the name of inventor Thaddeus J. Gabara and entitled “Comparator Circuits Having Non-Complementary Input Structures,” which is hereby incorporated by reference herein. This U.S. Patent Application describes a number of exemplary comparator circuits which provide substantial improvements relative to conventional circuits in terms of reduced power dissipation, transistor count and throughput delay. In an illustrative embodiment described therein, the above-described problem relating to leaving non-complementary inputs connected during an evaluation mode is addressed through the use of multiple non-complementary clock signals. However, such an approach typically requires additional circuitry and careful control of related timing and delay issues.
Despite the considerable advancements provided by the circuits described in the above-cited U.S. Patent Application, a need remains for further improvements in these and other types of data capture circuits. For example, improved techniques are needed for the sampling of non-complementary input signals in data capture circuit applications, so as to avoid the additional circuitry, timing and delay issues associated with the above-described multiple clock signal approach.
SUMMARY OF THE INVENTION
The present invention meets the above-identified need by providing data capture circuits having improved sampling structures.
In accordance with one aspect of the present invention, a data capture circuit includes a series channel sampling structure coupled to an evaluation element such as a memory cell. The series channel sampling structure includes a plurality of series-connected transistor devices configured for operation under the control of at least one clock signal to connect an input signal, applied to an input of the series channel sampling structure, to an input of the evaluation element, and to subsequently disconnect the input signal from the input of the evaluation element.
Advantageously, the series channel sampling structure can be configured and clocked in a manner that ensures that connection of the input signal to the input of the evaluation element occurs only at or near transitions of the clock signal, such that power dissipation in the data capture circuit is reduced and its speed of operation can be increased.
In an illustrative embodiment of the invention, the series channel sampling structure comprises a pair of metal oxide semiconductor (MOS) transistors having their channels connected in series. For example, the series channel sampling structure may be a series P-N channel sampling structure comprising a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor having their channels connected in series. In this case, the same clock signal is preferably applied to gate terminals of both the PMOS and NMOS transistors. As another example, the series channel sampling structure may be a series N-N channel sampling structure or a series P-P sampling structure, each comprising a pair of NMOS or PMOS transistors having their channels connected in series. In this case, a first clock signal may be applied to a gate terminal of one of the transistors and a complemented version of the first clock signal may be applied to a gate terminal of the other transistor.
In accordance with another aspect of the invention, in an embodiment in which the series channel sampling structure comprises a pair of MOS transistors having their channels connected in series, a first clock signal is applied to a gate terminal of a first one of the MOS transistors and a complemented version of the first clock signal is applied to a gate terminal of the other MOS transistor. An amount of delay may be introduced between a transition of the first clock signal and a corresponding transition in the complemented version of the first clock signal, such that the series channel sampling structure remains conductive after the transition of the first clock signal for a period of time corresponding to the amount of introduced delay.
In accordance with a further aspect of the invention, the data capture circuit may comprise a first series channel sampling structure coupled to a first node of the evaluation element and a second series channel sampling structure coupled to a second node of the evaluation element, with each of the series channel sampling structures being operative to connect and disconnect a corresponding input signal from the associated node of the evaluation element under the control of at least one clock signal. The input signals may be non-complementary input signals.
The invention can be used to implement flip-flops, memory cells and latches, as well as sense amplifiers and other types of comparators, having reduced power consumption and improved speed of operation.


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