Data capture circuit with self-test capability

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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Reexamination Certificate

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09947684

ABSTRACT:
A data capture circuit having a self-test capability includes a first data capture element to be tested in a self-test mode of operation, at least one additional data capture element, e.g., a second data capture element that is a substantial duplicate of the first, a clock generator circuit, a controller and a comparison circuit. The clock generator circuit is configured to generate a clock signal for application to clock inputs of the data capture elements, and a number of selectable clock-based test data signals. In the test mode, the controller selects at least a particular one of the test data signals for application to a data input of the first data capture element. A delayed version of the selected test data signal is applied to a data input of the second data capture element. The comparison circuit is configured to compare output signals generated by the first and second data capture elements, and supplies a result of the comparison back to the controller. The controller repeats the selection of particular test data signals and monitors corresponding comparison results until set-up and hold times or other clocking characteristics of the first data capture element are determined to a desired level of accuracy.

REFERENCES:
patent: 5729550 (1998-03-01), Nakajima et al.
patent: 6493408 (2002-12-01), Kobayashi
U.S. Appl. No. 09/374,258, filed Aug. 13, 1999, T.J. Gabara et al., “Signal Processing Method and Apparatus For Ensuring a Desired Relationship Between Signals.”
T. Xanthopoulos et al., “The Design and Analysis of the Clock Distribution Network for a 1.GHz Alpha Microprocessor,” ISSCC 2001, 2 pages, Feb. 2001.

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