Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-12-12
2004-04-27
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S496000, C708S550000
Reexamination Certificate
active
06728739
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a device for processing data in a data block unit configured by obtaining a data group containing one or more pieces of data, and furthermore containing multiple data groups, and more specifically to a block-floating-point type digital signal processor (hereinafter referred to as a DSP for short) for performing a fixed-point calculation in a block-floating-point system.
BACKGROUND ART
There is fixed-point representation or floating-point representation as a method of representing a value in a digital signal processing.
In the floating-point representation, each piece of data has an exponent and a mantissa, thereby guaranteeing high precision and a wide dynamic range. However, it also has a problem of requiring complicated and large-scale hardware.
On the other hand, in the fixed-point representation, only simple and small-scale hardware is required, but there is a problem of the degradation in calculation precision.
FIG. 10
shows an example of a typical conventional fixed-point type DSP.
FIG. 10
actually shows a configuration of a conventional fixed-point type DSP, and the number of bits of the data in the input/output stage of each component.
As shown in
FIG. 10
, the conventional fixed-point type DSP includes a data memory
100
for storing data in n bit length, a multiply-accumulate operation unit
12
for receiving n bit data from the data memory
100
and outputting 2n bit calculated data, a selection circuit
13
for selecting higher n bit data from the 2n bit calculated data, and a data bus
110
. The DSP reads data which is to be computed from the data memory
100
, calculates the read data in the multiply-accumulate operation unit
12
, selects by the selection circuit
13
the higher n bit data from the calculated data received from the multiply-accumulate operation unit
12
, and stores again the calculated data from the selection circuit
13
in the data memory
100
.
The multiply-accumulate operation unit
12
includes a first register file
12
a
for holding data from the data memory
100
, a multiplier
12
b
for multiplying the data from the first register file
12
a
, an adder
12
c
for adding the multiplied data from the multiplier
12
b
to sum data obtained up to this time, and a register file
12
d
for holding the sum data from the adder
12
c
as calculated data.
The degradation of the calculation precision occurs by truncation of the lower n bits when the selection circuit
13
selects the n bits from the 2n bits.
The degradation of the calculation precision in the fixed-point representation is explained by using the following equations (1) and (2). That is, the multiply-accumulate operation unit
12
performs operations by the following equations (1) and (2).
For simple explanation, the data from the data memory
100
is taken as 8 bits, the output from the multiply-accumulate operation unit
12
as 16 bits, and the data X(
0
) to X(
7
) and the coefficient data A(
0
) to A(
3
), B(
0
), and B(
1
) are provided for calculation for the multiply-accumulate operation unit
12
. The data X(
0
) to X(
7
) and the coefficient data A(
0
) to A(
3
), B(
0
), and B(
1
) respectively have the values as shown in
FIG. 11
, and X(−3)=X(−2)=X(−1)=Y(−1)=0. Furthermore, as shown in
FIG. 12
, the most significant bits (MSB) of each data and coefficient data are sign bits, and a binary point is placed between the sign bit and a right adjacent bit. The right adjacent bit of the sign bit has significance of 0.5, and the decimal representation of the values of each piece of data and coefficient data is shown in FIG.
11
.
FIG. 13
shows an operation result obtained when an operation is performed by the following equations (1) and (2) using the conventional fixed-point type DSP.
FIG. 13
also shows an operation result (binary representation and decimal representation) finally stored in the data memory
100
, the output (16-bit binary representation) of the multiply-accumulate operation unit
12
as an intermediate result, and an operation result obtained when an operation is performed using a floating-point for comparison. Since the data of lower 8 bits is lost when 8 bits are selected from 16 bits, the precision is lowered. A signal-to-noise ratio (SNR) is introduced as a scale indicating the amount of degradation in precision, and is defined by the following equation (3).
The following equation (3) shows an operation performed by dividing a sum of squares of a result of a floating-point operation result by a sum of squares of an error (difference between a result of a fixed-point operation and a result of a floating-point operation). A smaller value indicates lower precision. When the SNR is computed using the result shown in
FIG. 13
, the result is obtained by the following equations (4) and (5). The following equation (4) shows the SNR based on the operation result of the following equation (1). The following equation (5) shows the SNR based on the operation result of the following equation (2).
Thus, in the fixed-point representation, the precision considerably drops with the repetition of continuous operations.
The block-floating-point system has been developed to solve the above mentioned problem. In this system, a predetermined number (m, for example) of pieces of data is defined as a data block, a block scale factor is assigned to one data block, and a joint scaling (hereinafter referred to as block normalization) is performed on pieces of data in the data block, thereby reducing the degradation in precision by effectively using a limited dynamic range.
To efficiently realize the block-floating-point, for example, a DSP as shown in
FIG. 14
is suggested (Japanese Patent Laid-Open No. 10-40073).
In addition to the configuration of the above mentioned conventional fixed-point type DSP, the block-floating-point type DSP includes, as shown in
FIG. 14
, the second shifter
10
for block-normalizing the input data to the multiply-accumulate operation unit
12
based on a given scale factor; a block scale factor detector
54
for detecting a block scale factor based on each piece of the data contained in the data block; and a block scale factor register
56
storing the block scale factor.
The block scale factor detector
54
receives the calculated data from the selection circuit
13
, detects the data whose absolute value is the largest in all data of the data block, and the detected number of redundant bits is detected as a block scale factor.
When a second shifter
10
receives the block scale factor of the block scale factor register
56
from the control device not shown in the drawings, the second shifter
10
shifts bits by the amount corresponding to the block scale factor to the higher bit direction for each piece of data of the data block (hereinafter, referred to as left shift).
Next, the operations performed when the following equations (1) and (2) are used in the above mentioned conventional block-floating-point type DSP are described below.
First, the number of pieces of data contained in the data block is defined as a ‘block size’, and a series of processes in which each piece of data in the data block is read from the data memory
100
, a multiply-accumulate operation is performed on the data, and then the calculated data which is an operation result is stored in the data memory
100
again are defined as ‘block processes’.
In the following equations (1) and (2), an operation is performed by the following equation (1) with the block size of
8
and an input of the data blocks X(
0
) to X(
7
) in the first block process to obtain Y(
0
) to Y(
7
), and an operation is performed by the following equation (2) with the block size of
8
and an input of the data blocks Y(
0
) to Y(
7
) in the second block process to obtain Z(
0
) to Z(
7
). In the first block process, since the block scale factor of 0 is set in the block scale factor register
56
, the block normalizing process is not performed by the second shifter
10
. In the following descriptio
Fettweis Gerhard
Kobayashi Shiro
Asahi Kasei Kabushiki Kaisha
Malzahn David H.
LandOfFree
Data calculating device and method for processing data in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data calculating device and method for processing data in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data calculating device and method for processing data in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3252373