Data caching and address translation system with rapid turnover

Details Data caching and address translation system with rapid turnover Data caching and address translation system with rapid turnover

1991-02-22

1994-02-01

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 364DIG1, G06F 1206

Patent

active

052838820

ABSTRACT:
An address couple associateive memory (ACAM) for a processor in a chip package provides a first address couple (ACL) CAM and a second absolute address list (AAL) CAM. An associated control unit guarantees coherency of word data in a cache RAM and main memory by indicating the invalidity or validity of each location of address data in the first CAM (ACL) and second CAM (AAL). Each loaction of data words in the cache RAM is associated with a corresponding location in the first (ACL) CAM and in the second (AAL) CAM. Address translation is provided in one clock cycle when writing to a location in main memory specified by a logical address couple.

REFERENCES:
patent: 4669043 (1987-05-01), Kaplinsky
patent: 4763250 (1988-08-01), Keshlear et al.
patent: 4797817 (1989-01-01), Nguyen et al.
patent: 4980816 (1990-12-01), Fukuzawa et al.
patent: 5053951 (1991-10-01), Nusinov et al.
patent: 5133058 (1992-07-01), Jensen

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