Data cache memory internal circuitry for reducing wait states

Details Data cache memory internal circuitry for reducing wait states Data cache memory internal circuitry for reducing wait states

1995-03-21

1996-11-19

Chan, Eddie P.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365195, 364DIG1, 36424341, 395488, G06F 1202

Patent

active

055772250

ABSTRACT:
The mechanism for performing writes to the data cache in a cache subsystem is modified to reduce the occurrence of microprocessor wait states. Concurrently, with operation of the tag RAM, the write signal from the microprocessor propagates through the data cache up to a point in the internal circuitry of the data cache which is as close as reasonably possible to the memory cell being written. At this point in the circuitry, the write signal is gated by the Match signal from the tag RAM. If the tag RAM generates a "hit" Match output signal, the write is allowed to finish propagating through data cache internal circuitry without additional address set-up time. This allows the memory cell to be written to quickly and reduces the probability of microprocessor wait states.

REFERENCES:
patent: 4912626 (1990-03-01), Fiacconi
patent: 5247642 (1993-09-01), Kadlec et al.
patent: 5329632 (1994-07-01), Lee et al.
patent: 5353427 (1994-10-01), Fujishima et al.
patent: 5423014 (1995-06-01), Hinton et al.

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