Data cache management system with test mode using index register

Details Data cache management system with test mode using index register Data cache management system with test mode using index register

1990-07-02

1994-01-04

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 371 211, 371 216, 395400, G06F 1122

Patent

active

052768333

ABSTRACT:
A memory controller which can be used with an external tag RAM is disclosed. Existing index registers in the controller serve double duty as buffers for storing tag RAM data during a test mode. Input/output lines for the external tag RAM are coupled to the index registers in addition to being coupled to a comparator for comparison with an external address during normal operation. A buffer is provided so that data from the external address from the CPU can be written through these same tag RAM input/output lines in order to update the tag RAM after a miss. In order to prevent DRAMS from putting data on the memory bus during a cache RAM test, a CAS inhibit signal is provided to the DRAM state machine. Posted writes are also disabled to avoid interference with the address provided to the tag RAM.

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